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Registered: ‎04-06-2018

Constant constants

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What should the VHDL constant -20sd"500000" synthesize to when assigning inside a signed adder?

 

I have my opinion.  Vivado has its opinion.  I thought constants were supposed to be free of opinion.

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Scholar
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Registered: ‎08-01-2012

Re: Constant constants

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It should cause an error, as sd is not a valid bit string literal identifier. From the 2008 Spec:

bit_string_literal ::= [ integer ] base_specifier " [ bit_value ] "
bit_value ::= graphic_character { [ underline ] graphic_character }
base_specifier ::= B | O | X | UB | UO | UX | SB | SO | SX | D

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Scholar
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Registered: ‎08-01-2012

Re: Constant constants

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It should cause an error, as sd is not a valid bit string literal identifier. From the 2008 Spec:

bit_string_literal ::= [ integer ] base_specifier " [ bit_value ] "
bit_value ::= graphic_character { [ underline ] graphic_character }
base_specifier ::= B | O | X | UB | UO | UX | SB | SO | SX | D

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Visitor
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Registered: ‎04-06-2018

Re: Constant constants

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Thanks.  Perhaps it caused a warning; too hard to tell when hundreds of warning come up in any one synthesis.

 

So to assign a signed value in human readable form (-500000 is so much more obvious than 0x85ee0) means I'm pretty much out of luck without doing a to_signed conversion or just resorting to the hex value (which I did).

I'm used to Verilog (about 15 years focused experience) and am saddened by the contortions required to do simple arithmetic or apply constants in VHDL.

I wish there was a way to know it was bad syntax!

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Registered: ‎04-26-2012

Re: Constant constants

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@johnhandwork   "to assign a signed value in human readable form (-500000 is so much more obvious than 0x85ee0) means I'm pretty much out of luck"

Perhaps you could post a complete example of the usage problem you're having.

With numeric_std, it's fairly straightforward to define constants and also to use signed integers within signed expressions, see example below.

> I'm used to Verilog <snip> and am saddened by the contortions required to do simple arithmetic or apply constants in VHDL.

Ahhh, Verilog... the language that zero extends signed constants :)

-Brian

--
-- VHDL-2008 signed constant examples using numeric_std
--

library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;

entity test_signed_constants is
  generic
  (
    WIDTH : natural := 20
  );
  port 
  ( 
    clk      : in  std_logic;
    sync_rst : in  std_logic;
    accum    : out signed(WIDTH-1 downto 0)
  );
end test_signed_constants;

architecture arch1 of test_signed_constants is

  --
  -- integer decimal constants
  --
  constant  THRESHOLD : integer := -50_000;
  constant  INC       : integer := -3;

  --
  -- signed decimal constants
  --
  constant  INIT_A     : signed(WIDTH-1 downto 0) := to_signed( -49_996, WIDTH);   -- to_signed() of decimal value

  constant  INIT_B     : signed(WIDTH-1 downto 0) := -20D"49_990";                 -- VHDL-2008 decimal bit string constant


begin

 process
   begin

     wait until rising_edge(clk);

     if sync_rst = '1' then
       accum <= INIT_A;

     elsif accum < THRESHOLD then   -- comparison, signed < integer
       accum <= INIT_B;             

     else
       accum <= accum + INC;        -- arithmetic, signed + integer

     end if;

   end process;

end arch1;

 

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