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08-31-2018 05:00 AM
I have a source differential clock clk125 :
input clk125_p_i , input clk125_n_i ,
in constraints it's defined as :
set_property PACKAGE_PIN F21 [get_ports "clk125_n_i"] set_property IOSTANDARD LVDS_25 [get_ports "clk125_n_i"] set_property PACKAGE_PIN G21 [get_ports "clk125_p_i"] set_property IOSTANDARD LVDS_25 [get_ports "clk125_p_i"] create_clock -period 8.000 -name clk125 [get_ports clk125_p_i]
In implementation report on timing all is ok :
Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- clk125 {0.000 4.000} 8.000 125.000
This clock transfer to IBUFDS to make it single-ended clock source.But in the report, I see that the synthesizer has changed the value of the clock.
Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- i_wrapper/design_1_i/util_ds_buf_0/U0/IBUF_OUT[0] {0.000 5.000} 10.000 100.000
I have tried to reassign in constrain file value of this clock but not effect. In report i've get message like
CRITICAL WARNING: [Constraints 18-851] Could not find an automatically derived clock matching the supplied criteria for renaming.
What is wrong?
08-31-2018 05:25 AM
Hi, @darky777 ,
It seems there is other create_clock constraint in the design also work on the port.
You can run the below command after openning the synthesized design:
write_xdc tt.xdc
In the generated tt.xdc, you can check which line of constraint conflict with your original create_clock constraint.
08-31-2018 06:18 AM
Thank you @hongh for reply.
Other constraints contain create_clock for output in IP Utility Buffer, that i've called. I've rewrited it.