05-29-2014 04:55 PM
I am having issues with my contraints. What I want to achieve is to map my RAM32X8S to a single slice and I want to be able to specify where the slice is located on the FPGA. I tried the following attributes declared in VHDL:
ATTRIBUTE LOC of RAM32X8S_inst: label is "SLICE_X0Y0 "; ATTRIBUTE BLKNM of RAM32X8S_inst: label is "BLOCK_NAME" ;
This seemed to work somewhat. The BLKNM maps the RAM to a single slice, but the LOC constraint is ignored and the slice is situated at random positions on the FPGA and it doesn't matter what I specify in the ATTRIBUTE. Now I've added a PowerPC core to the design, and now the both these ATTRIBUTEs are ignored.
As a result, I tried placing the constraints in a ucf, but this is also ignored:
INST inst_RAM/RAM32X8S_inst BLKNM="BLOCK_NAME"; INST inst_RAM/RAM32X8S_inst LOC="SLICE_X0Y0";
and I've also tried
INST inst_RAM/RAM32X8S_inst LUTNM="BLOCK_NAME" ;
But nothing seems to work. I also tried with the "inst_name" with quotation marks, but the constraint is still ignored.
As you can see, my hierarchy is as follows Top -> inst_RAM -> RAM32X8S_inst.
I don't receive any warnings during the Implementation, but when I open the design with FPGAeditor, I don't find any block named BLOCK_NAME and the RAM is distributed accross the FPGA floorplan.
I am using ISE 13.4 and a Virtex-5 FPGA.
Why are my constraints ignored? Could anyone please provide some advice?
05-30-2014 01:49 AM
very odd that you don't get any warning during Translate or MAP.
Can you try to open the design in PlanAhead and move and lock the primitive and save the constraints?
05-30-2014 01:57 AM
Thank you very much for the reply. It is very funny indeed. When I open the design in PlanAhead, it shows the RAM at the specified location and it is highligted in red. When I go to its properties, it shows that the constraint is locked (I assume thats the reason for the red highlight), but nothing is routed to this component. It is almost as if it is trimmed away. Again, I can't find any warning on this, and I have added the flag not to trim unconnected signals - just in case. Could it be an issue with optimization? Maybe the component is optimized, so the site is not required?
06-02-2014 04:33 AM
Sorry for the double post, but I just wanted to give some feedback. The problem was that the component I was trying to place was trimmed to such an extend that the component was reduced to a couple of nets. As a result, the constraints were ignored. The BLKNM constraint works and I am able to find my slice, but the LOC constraint is ignored (for some reason). Any idea why that is?