08-19-2016 04:35 AM
Hi, I have problems with my counter. Sorry for my poor english Register should be reset on the posedge of signal x1 and should be increased on the posedge of CLOCK. I know that register can be changed only in one always process, but I don't know how do that. The error is:
Line 33: Signal register in unit blagam_o_synteze is connected to following multiple drivers:
08-19-2016 04:49 AM
08-19-2016 04:58 AM
//multiple issue with code . refer this example
module first_counter (
clock , // Clock input of the design
reset , // active high, synchronous Reset input
enable , // Active high enable signal for counter
counter_out // 4 bit vector output of the counter
); // End of port list
input clock ;
input reset ;
input enable ;
output [3:0] counter_out ;
//-------------Input ports Data Type-------------------
// By rule all the input ports should be wires
wire clock ;
wire reset ;
wire enable ;
//-------------Output Ports Data Type------------------
// Output port can be a storage element (reg) or a wire
reg [3:0] counter_out ;
//------------Code Starts Here-------------------------
// Since this counter is a positive edge trigged one,
// We trigger the below block with respect to positive
// edge of the clock.
always @ (posedge clock)
begin : COUNTER // Block Name
// At every rising edge of clock we check if reset is active
// If active, we load the counter output with 4'b0000
if (reset == 1'b1) begin
counter_out <= #1 4'b0000;
// If enable is active, then we increment the counter
else if (enable == 1'b1) begin
counter_out <= #1 counter_out + 1;
end // End of Block COUNTER
endmodule // End of Module counter
08-19-2016 05:07 AM
It's expected from the code. Let's look into your code.
You have 2 always block in which
ENABLE and register value is changed. There is a possibility that both the event posedge(x1) and posedge(CLK) occurs at the same time and if ENABLE=1 then reg is assigned 2 values.
According to below loop register value is 0
always @(posedge x1)
register <= 12'd0;
whereas according to
always @(posedge CLOCK)
register <= register + 1;
register value is incremented(Conflicting with the 1st one).
It will lead to multidriver issue.
You can put these into a single always block and use if statement to give priority of the event.
08-19-2016 05:58 AM - edited 08-19-2016 06:06 AM
Lets go back and think about what it is you are asking the tool to do.
You are trying to describe a portion of a system that changes its state on the rising edge of two different clocks. Remember that synthesis is creating a circuit using real hardware cells that exist on the FPGA.
You always have to think hardware. So, I ask you - what real hardware cell do you know that can change its state on the rising edge of two different clocks. The answer is "there is no such thing" (at least in an FPGA and most modern digital technologies).
So, the simple answer as to why synthesis is complaining about your code is that you are asking it to do something impossible. It's not a coding thing or a synthesis thing, its a conceptual thing.
So, go back and now ask yourself - "what do I really want to do"? And then "how can I implement that will cells that exist in the FPGA technology" (which are combinatorial cells and flip-flops), and then describe what you want in RTL code.
Maybe if you give us a some more details about what you want to accomplish (not about how you are trying to do it) we might be able to give you more helpful answers. Why do you want a counter to reset on the rising edge of one "clock"? What are the frequencies of the clocks? ...
08-19-2016 01:09 PM
I want to accomplish phase detector between signals x1 and x2. Their frequencies are about 1kHz. I want to count impulses of CLOCK between their rising edges. So I wanted to start counting on rising edge of x1 and finish counitng on rising edge of x2. On the next rising edge of x1 I want to start counting from the beginning so I reset the counter. Of course, the frequency of the CLOCK is much much higher for example 100 MHz.
08-20-2016 05:45 PM