cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
accacca
Visitor
Visitor
550 Views
Registered: ‎08-16-2018

Create a clock divide signals array in VHDL - wrong schematic

I want to get some enable signals to divide the frequency of the main clock.
my idea is to create a signal vector to use as a clock enable signals

These clock enable signal remains at 1 for a single half period centered on the rising edge of the main clock
Each of these signals is repeated every two or every four or every eight ....clock pulses thus allowing to obtain lower frequencies synchronous with the main clock.

Perhaps an image clarifies the things better see simulation.jpg
CLK_OUT [0] is an enable signal with frequency CLK / 2
CLK_OUT [1] is an enable signal with frequency CLK / 4

But when I have checked the schematic I have found a problem: why the adder output is unconnected ?

Tags (2)
schematic.jpg
simulation.jpg
0 Kudos
Reply
7 Replies
drjohnsmith
Teacher
Teacher
542 Views
Registered: ‎07-09-2009

interesting code,
interesting using that old a ISE,
interesting using a negative edge clock, why ?

What do you want this code to do ?

clk_upd : process (count0SP, count1SP) is
begin
count0SN <= count1SP ;
count1SN <= count1SP+1 ;

Its an interesting bit of code, which I must admit got me tied up trying to read on the phone screen.

the normal way of doing this is a single counter,

which you decode to give the single output bit you want.

If you want to work it out, Have look in the simulation as to what the other std_logic vectors are up to,

and to prove things look at post synthesis simulation,

but personally, I'd make the enables a full clock wide, so the set up and hold is correct on the registers, and just decode them of a single counter.




<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
515 Views
Registered: ‎01-22-2015

@accacca 

A clock should not be routed through combinational logic (eg. AND-gates, XOR-gate, LUTs)  -  because, the resulting clock will degrade the timing analysis performance of your design.

A better way to create a divided-down clock is to route a base clock through a BUFGCE clock buffer and to use your counting-logic to toggle the clock-enable (CE) pin of the BUFGCE as shown by Avrum in the following thread.

https://forums.xilinx.com/t5/Timing-Analysis/Divided-clock-constraints/m-p/863501#M14336

Also in the above thread, read Avrum's comments about writing a create_generated_clock constraint for the divided-down clock.

Cheers,
Mark

0 Kudos
Reply
accacca
Visitor
Visitor
489 Views
Registered: ‎08-16-2018


A clock should not be routed through combinational logic (eg. AND-gates, XOR-gate, LUTs)  -  because, the resulting clock will degrade the timing analysis performance of your design....


Mark I disagree I don't send the clock signal through the logic but I create  enable signals array synchronous with the clock
I'll use it like this
 

 

if CLOCK'event and CLOCK = 1 then
  if CLK_OUT [0] = 1 then
    here frequency half of master clock
    replacing [0] with [1] or [x] divide CLOCK for 2^(X + 1)
  endif
endif

CLK_OUT is probably not a correct name for the array variable

I could have the uncertainty about the timing on the fronts indicated by the red circles but the enable signal is stable on the CLOCK front.

 

 
simulation1.jpg
 
 
 
 
 
 
 
 
 
 
 
 
 
 
My task is facilitated by the fact that I work on projects for industrial automation systems and in my case a very high frequency is not required, I am far from the limits of the component.

Thank you for the reply I will read the thread you reported to understand how things must be done correctly.
 
drjohnsmith
Teacher
Teacher
476 Views
Registered: ‎07-09-2009

Going back to your code,
your aim is to make a counter with
count1SN <= count1SP+1
Is that your intention ?

If so one problem you have is both these signals are std_logic_vector,
and in ISE , you can not do std_logic_vector + 1

Just to state the obvious, you are describing hardware, and the more "standard" you can describe things, the easier the tools will find it.

If I have understood the first part,
the way to do a counter is

signal my_counter : unsigned( N-1 downto 0) := (others => '0');

Process ( clk )
begin
if rising_edge( clk ) then
my_counter <= my_counter +1 ;
end if;
end process;

Notes. In an FPGA you do not need a reset very often, This is one case where you defiantly don't need a reset, unless absolute phase at start up is essential, ( it rarely is )

Also note, unsigned, you CAN add one to using the std libs in ISE 8 you have.

Try that as a start,
and get back to the forum,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Reply
richardhead
Scholar
Scholar
475 Views
Registered: ‎08-01-2012

The code you have written for this feels a bit strange. Usually it is simplest to have a counter and compare to a known value. Usually 0 because it is a simpler compare operation (you can simply or all of the bits and invert the output).

For you project, why not simply have a larger counter and and compare the specific bits needed to 0?

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clkdivide is
  generic ( N       : integer := 10) ;
  port    (
            RESET       : in  STD_LOGIC;
            CLOCK       : in  STD_LOGIC;
            CLK_OUT_EN  : out STD_LOGIC_VECTOR (N-1 downto 0)
          );
end entity clkdivide;

architecture rtl of clkdivide is
  signal en_cnt   : unsigned(N-1 downto 0);
begin

  cnt_proc : process(clk, reset)
  begin
    if reset = '1' then
      en_cnt      <= (others => '0');
      CLK_OUT_EN  <= (others => '0');

    elsif falling_edge(clk) then
      en_cnt      <= en_cnt + 1;
      CLK_OUT_EN  <= (others => '0');  -- default is '0'

      for i in CLK_OUT_EN'range loop
        if en_cnt(i downto 0) = 0 then
          CLK_OUT_EN(i)   <= '1';     -- Enable is high every 2^(i+1) clock. 
        end if;
      end loop;
    end if;
  end process;
end architecture;

 

0 Kudos
Reply
bruce_karaffa
Scholar
Scholar
468 Views
Registered: ‎06-21-2017

Why must the clock enables be active for only half of the master clock cycle?  This adds to the complexity of the circuit and should not make a difference to any following synchronous circuit?

0 Kudos
Reply
461 Views
Registered: ‎01-22-2015

@accacca 

Mark I disagree I don't send the clock signal through the logic but I create  enable signals array synchronous with the clock
I'll use it like this..

My mistake!  Apologies to you and @drjohnsmith for interrupting the good advice you are getting from him.

 

...but, now that I'm here...

Yes, the use of clock enables as you describe is a great tool - and they are often preferred to slow clocks.   

 

But when I have checked the schematic I have found a problem: why the adder output is unconnected ?

FYI - I get the same elaboration schematic as yours when using Vivado v2018.3.  

Document UG949 is the Xilinx list of “best practices” for doing FPGA work.  UG949 says little about using and working with the Vivado elaborated design results – other than to open the elaborated design and run DRC and methodology checks.  On your design, these checks report no violations were found.

I have previously seen problems like this with Vivado elaboration schematics (ie. sometimes the schematics just seem wrong).  However, when Vivado synthesis and simulation are saying all-is-well, then I ignore elaboration schematics and move forward with the design. 

Cheers,
Mark

0 Kudos
Reply