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Visitor
Visitor
658 Views
Registered: ‎02-06-2018

Create sixteen 80-bit registers

Greetings,

 

I am trying to create sixteen many 80-bit registers and I don't want to instantiate the register block 16 times. So I made the following.  Looking at the waveform, it seems only create one 16-bit register.    Could anyone guide what is the issue of the code or how this suppose to be implemented?    Thanks in advance. 

 

CH

 

-- code start 

-- signal declearation

type dataregoutput_type is array(0 to 15) of std_logic_vector(79 downto 0);
signal dataregout : dataregoutput_type;

 

-- functional code

gen_dataregen: for i in 0 to 15 generate
dataregen(i) <= (addren(2) or initregout(0)) and decoder_4_to_16_out(i);

U_Register: entity work.Register(Registerbhv)
generic map(width => 80)
port map(
CE => dataregen(i),
D => datain,
Q => dataregout(i),
Clock => clkctrl,
Reset => Reset);
end generate;

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Teacher
Teacher
641 Views
Registered: ‎07-09-2009

Re: Create sixteen 80-bit registers

look up arrays , 

and the generate statment, as in for i in 0 to 15 generate

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Mentor
Mentor
614 Views
Registered: ‎02-24-2014

Re: Create sixteen 80-bit registers

your code looks more or less OK,  you should load the synthesized design in Vivado, and then check the schematic to see if the registers have been created. 

Don't forget to close a thread when possible by accepting a post as a solution.
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