08-14-2018 07:38 AM
Hi all, I have been having some trouble producing EDIF versions of some VHDL files. My process so far is to systhesise the desing and use the write_edif function to produce the netlist files and then put these back into the original design. However when trying to resynthesise the design I get the error:
[Netlist 29-77] Could not replace (cell '###', library 'work', file 'NOFILE') with (cell '###', library 'work', file '###.edn') because of a port interface mismatch; 114 ports are missing on the replacing cell.
This seems to be due to multidimensional signals used within the design and I followed advice given on https://www.xilinx.com/support/answers/70089.html however this seems to have little to no effect. It is not possible to change the top file to accommodate the changes in names as it must remain the same. Is there an alternative solution that prevents these name changes?
08-20-2018 08:58 AM
Have you tried using design checkpoint (DCP) files instead of an EDIF netlist? Functionally they are pretty much the same, but you might get around the naming problem.
08-20-2018 01:36 PM
What is it you are trying to do?
If your goal is to provide a student "project" with some portions of the design already synthesized, then edif is probably not the way to go.
Vivado fully supports "out-of-context (OOC)" synthesis. Any sub-module (and, with some effort, even the "top") can be synthesized on its own to create an out-of-context .dcp file.
When the full design is to be assembled, the remaining RTL files are also synthesized out-of-context, then all the other OOC .dcp files are read back in (with read_checkpoint). With this done, the complete synthesized design is available, and implementation can begin.
Originally, this flow was only supported in "non-project" mode (in fact, even fully OOC place and route was supported in non-project mode). But in the later versions of Vivado OOC synthesis for user modules is also supported in project mode (I have only "lightly" played with it) - but synthesis only; not place and route.
So give us a more complete description of what you are trying to accomplish, and maybe we can suggest a flow that does what you are trying to do.
08-23-2018 02:16 PM
Thanks for your help so far, I will look into dcp files tomorrow (Late in UK) and report back. The aim is to provide students with "black-box" versions of a "perfect" design to allow the students to work simultaneously in groups on each producing one of the modules used in the final design. These modules are designed and simulated in ModelSim before being moved over to Vivado for synthesis and implementation onto the target device.
Therefore these "Black-box" modules either should be suitable for use in both simulation and synthesis or two different black box designs could be provided, one pre-synthesized and one for use in simulations.