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pavel_47
Voyager
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Registered: ‎05-30-2018

Critical warning: two global buffers on clockpath

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Hello,

In my design there two mutually exclusive clocks.

In order to handle them properly I was advised to include explicitely BUFGMUX. Here below is the link on the conserned post.

Timing constraints for multiplexed clocks

Synthesis tool added implicitely another buffer BUFG (please see the screenshot below).

The implementation tool did not like giving a critical warning:

[Place 30-461] A non-muxed BUFG 'design_1_i/logic_v_0/U0/i_logic_vhdl/inst_spi_slave/sck_BUFG_inst' is driven by another global buffer 'design_1_i/logic_v_0/U0/BUFGMUX_inst'. Remove non-muxed BUFG if it is not desired.

spis_sck_path_with_two_buffers.png

Why such warning is critical ?

Thanks

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pavel_47
Voyager
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Registered: ‎05-30-2018

Oddly, after a modification of the code, not related to the mentionned problem, I redid the synthesis and the 2nd buffer is gone.

View solution in original post

10 Replies
dpaul24
Scholar
Scholar
1,484 Views
Registered: ‎08-07-2014

@pavel_47,

[Place 30-461] A non-muxed BUFG 'design_1_i/logic_v_0/U0/i_logic_vhdl/inst_spi_slave/sck_BUFG_inst' is driven by another global buffer 'design_1_i/logic_v_0/U0/BUFGMUX_inst'. Remove non-muxed BUFG if it is not desired.

I think the BUFGMUX is capable of driving a clock tree.

Have you tried removing i_logic_vhdl inst and see what happens?

 

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pavel_47
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i_logic_vhdl contains 99.9% of design.

Probably move BUFGMUX inside i_logic_vhdl ?

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pavel_47
Voyager
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Registered: ‎05-30-2018

Oddly, after a modification of the code, not related to the mentionned problem, I redid the synthesis and the 2nd buffer is gone.

View solution in original post

hongh
Moderator
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Registered: ‎11-04-2010

Hi, @pavel_47 ,

In the source code of module inst_spi_slave, there is still clock mux code, which infers the LUT for MUX. Since I_l_sck clokc is not used in module inst_spi_slave, you can remove the clock mux code in module "inst_spi_slave". Then the BUFG(sck_BUFG_inst) will not be inferred.

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pavel_47
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No, there is no any mux in inst_spi_slave.

Actually it looks like this (after disparation of 2nd buffer):

spis_sck_path_with_two_buffers_resolved.png

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viviany
Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

Looks to me some problem prevents cross-hierarchy optimization around inst_spi_slave. 

However, we won't know without reproducing the issue.

Fortunately it works now.

-vivian

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graces
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Registered: ‎07-16-2008

What is the LUT3 that drives the BUFG supposed to do? From the schematic, the other two input pins are tied to GND.

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pavel_47
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If you refer to the 1st picture, it does not exist anymore

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hongh
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Registered: ‎11-04-2010

Hi, @pavel_47 ,

Since the issue can not be reproduced again, please close the thread.

If you see the issue again, you can try to add dont_touch property on the output net of BUFGMUX as workaround and report the issue to us for further investigation.

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pavel_47
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Since the issue can not be reproduced again, please close the thread.

How can I do it ?

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