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Explorer
Explorer
3,249 Views
Registered: ‎05-14-2017

Custom AXI IP - VHDL error code

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Hello all,

 

I would like to the communication between CPU (through Linux OS) and FPGA, so I am creating a custom AXI slave IP core to functions as a ROM memory. The name of the IP is simoROM

 

Once I created my IP, two files are generated:

 

simoROM_v1_0.vhd

simoROM_v1_0_S00_AXI.vhd

 

I started editing the simoROM_v1_0.vhd as follows:

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity simoROM_v1_0 is
    generic (
        -- Users to add parameters here

        -- User parameters ends
        -- Do not modify the parameters beyond this line


        -- Parameters of Axi Slave Bus Interface S00_AXI
        C_S00_AXI_DATA_WIDTH    : integer   := 32;
        C_S00_AXI_ADDR_WIDTH    : integer   := 4
    );
    port (
        -- Users to add ports here

        -- User ports ends
        -- Do not modify the ports beyond this line


        -- Ports of Axi Slave Bus Interface S00_AXI
        s00_axi_aclk    : in std_logic;
        s00_axi_aresetn : in std_logic;
        s00_axi_awaddr  : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
        s00_axi_awprot  : in std_logic_vector(2 downto 0);
        s00_axi_awvalid : in std_logic;
        s00_axi_awready : out std_logic;
        s00_axi_wdata   : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
        s00_axi_wstrb   : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
        s00_axi_wvalid  : in std_logic;
        s00_axi_wready  : out std_logic;
        s00_axi_bresp   : out std_logic_vector(1 downto 0);
        s00_axi_bvalid  : out std_logic;
        s00_axi_bready  : in std_logic;
        s00_axi_araddr  : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
        s00_axi_arprot  : in std_logic_vector(2 downto 0);
        s00_axi_arvalid : in std_logic;
        s00_axi_arready : out std_logic;
        s00_axi_rdata   : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
        s00_axi_rresp   : out std_logic_vector(1 downto 0);
        s00_axi_rvalid  : out std_logic;
        s00_axi_rready  : in std_logic
    );
end simoROM_v1_0;

architecture arch_imp of simoROM_v1_0 is

    -- component declaration
    component simoROM_v1_0_S00_AXI is
        generic (
        C_S_AXI_DATA_WIDTH  : integer   := 32;
        C_S_AXI_ADDR_WIDTH  : integer   := 4
        );
        port (
        S_AXI_ACLK  : in std_logic;
        S_AXI_ARESETN   : in std_logic;
        S_AXI_AWADDR    : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
        S_AXI_AWPROT    : in std_logic_vector(2 downto 0);
        S_AXI_AWVALID   : in std_logic;
        S_AXI_AWREADY   : out std_logic;
        S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
        S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
        S_AXI_WVALID    : in std_logic;
        S_AXI_WREADY    : out std_logic;
        S_AXI_BRESP : out std_logic_vector(1 downto 0);
        S_AXI_BVALID    : out std_logic;
        S_AXI_BREADY    : in std_logic;
        S_AXI_ARADDR    : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
        S_AXI_ARPROT    : in std_logic_vector(2 downto 0);
        S_AXI_ARVALID   : in std_logic;
        S_AXI_ARREADY   : out std_logic;
        S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
        S_AXI_RRESP : out std_logic_vector(1 downto 0);
        S_AXI_RVALID    : out std_logic;
        S_AXI_RREADY    : in std_logic
        );

    -- ADDED BY SIMOZZ
    -- start simo custom block declaration
    -- declare 4 memory address each of 8 bit wide data type
    TYPE mymemory IS ARRAY (0 TO 7) OF STD_LOGIC_VECTOR (7 DOWNTO 0);
    CONSTANT myrom : mymemory := (
        0 => "10000000" ,
        1 => "01000000" ,
        2 => "00100000" ,
        3 => "00010000" ,
        4 => "00001000" ,
        5 => "00000100" ,
        6 => "00000010" ,
        7 => "00000001" 
    );
    -- end simo block declaration

    end component simoROM_v1_0_S00_AXI;

begin

-- Instantiation of Axi Bus Interface S00_AXI
simoROM_v1_0_S00_AXI_inst : simoROM_v1_0_S00_AXI
    generic map (
        C_S_AXI_DATA_WIDTH  => C_S00_AXI_DATA_WIDTH,
        C_S_AXI_ADDR_WIDTH  => C_S00_AXI_ADDR_WIDTH
    )
    port map 
    (
        S_AXI_ACLK  => s00_axi_aclk,
        S_AXI_ARESETN   => s00_axi_aresetn,
        S_AXI_AWADDR    => s00_axi_awaddr,
        S_AXI_AWPROT    => s00_axi_awprot,
        S_AXI_AWVALID   => s00_axi_awvalid,
        S_AXI_AWREADY   => s00_axi_awready,
        S_AXI_WDATA => s00_axi_wdata,
        S_AXI_WSTRB => s00_axi_wstrb,
        S_AXI_WVALID    => s00_axi_wvalid,
        S_AXI_WREADY    => s00_axi_wready,
        S_AXI_BRESP => s00_axi_bresp,
        S_AXI_BVALID    => s00_axi_bvalid,
        S_AXI_BREADY    => s00_axi_bready,
        S_AXI_ARADDR    => s00_axi_araddr,
        S_AXI_ARPROT    => s00_axi_arprot,
        S_AXI_ARVALID   => s00_axi_arvalid,
        S_AXI_ARREADY   => s00_axi_arready,
        S_AXI_RDATA => s00_axi_rdata,
        S_AXI_RRESP => s00_axi_rresp,
        S_AXI_RVALID    => s00_axi_rvalid,
        S_AXI_RREADY    => s00_axi_rready
    );

    -- ADDED BY SIMOZZ
    -- Add user logic here
    -- start simo custom block
    PROCESS (S_AXI_ACLK) BEGIN
        IF (S_AXI_ACLK'Event AND S_AXI_ACLK='1')
            S_AXI_WDATA <= myrom (s00_axi_araddr);
        END IF
    END PROCESS
    -- end simo custom block
    -- User logic ends

end arch_imp;

But the errrors listed in the attached files are fired up.

 

Could you help me to understand what's wrong in my VHDL code ?

Thank you in advance.

Simon

 

 

error.png
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1 Solution

Accepted Solutions
Moderator
Moderator
5,798 Views
Registered: ‎11-09-2015

Re: Custom AXI IP - VHDL error code

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Hi @simozz,

 

You need to do "end component simoROM_v1_0_S00_AXI;" after the component declaration:

 

    -- component declaration
    component simoROM_v1_0_S00_AXI is
        generic (
        C_S_AXI_DATA_WIDTH  : integer   := 32;
        C_S_AXI_ADDR_WIDTH  : integer   := 4
        );
        port (
        S_AXI_ACLK  : in std_logic;
...
        S_AXI_RREADY    : in std_logic
        );
        end component simoROM_v1_0_S00_AXI;
    -- ADDED BY SIMOZZ

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
6 Replies
Moderator
Moderator
5,799 Views
Registered: ‎11-09-2015

Re: Custom AXI IP - VHDL error code

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Hi @simozz,

 

You need to do "end component simoROM_v1_0_S00_AXI;" after the component declaration:

 

    -- component declaration
    component simoROM_v1_0_S00_AXI is
        generic (
        C_S_AXI_DATA_WIDTH  : integer   := 32;
        C_S_AXI_ADDR_WIDTH  : integer   := 4
        );
        port (
        S_AXI_ACLK  : in std_logic;
...
        S_AXI_RREADY    : in std_logic
        );
        end component simoROM_v1_0_S00_AXI;
    -- ADDED BY SIMOZZ

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Moderator
Moderator
3,239 Views
Registered: ‎11-09-2015

Re: Custom AXI IP - VHDL error code

Jump to solution

Hi @simozz,

 

In fact it is in your code, just at the wrong place.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Moderator
Moderator
3,225 Views
Registered: ‎11-09-2015

Re: Custom AXI IP - VHDL error code

Jump to solution

Hi @simozz,

 

Does your issue is fixed? If yes, could you mark one of the previous post as solution?

 

Thanks and Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Explorer
Explorer
3,221 Views
Registered: ‎05-14-2017

Re: Custom AXI IP - VHDL error code

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Hello @florentw

 

I am solving the issue. Yes the code you mentioned was not in the right place but I am fixing another error.

In my previuos code I was trying to send output data through an input port ... and I changed the code as follows:

 

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity simoROM_v1_0 is
    generic (
        -- Users to add parameters here

        -- User parameters ends
        -- Do not modify the parameters beyond this line


        -- Parameters of Axi Slave Bus Interface S00_AXI
        C_S00_AXI_DATA_WIDTH    : integer   := 32;
        C_S00_AXI_ADDR_WIDTH    : integer   := 4
    );
    port (
        -- Users to add ports here

        -- User ports ends
        -- Do not modify the ports beyond this line


        -- Ports of Axi Slave Bus Interface S00_AXI
        s00_axi_aclk    : in std_logic;
        s00_axi_aresetn : in std_logic;
        s00_axi_awaddr  : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
        s00_axi_awprot  : in std_logic_vector(2 downto 0);
        s00_axi_awvalid : in std_logic;
        s00_axi_awready : out std_logic;
        s00_axi_wdata   : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
        s00_axi_wstrb   : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
        s00_axi_wvalid  : in std_logic;
        s00_axi_wready  : out std_logic;
        s00_axi_bresp   : out std_logic_vector(1 downto 0);
        s00_axi_bvalid  : out std_logic;
        s00_axi_bready  : in std_logic;
        s00_axi_araddr  : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
        s00_axi_arprot  : in std_logic_vector(2 downto 0);
        s00_axi_arvalid : in std_logic;
        s00_axi_arready : out std_logic;
        s00_axi_rdata   : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
        s00_axi_rresp   : out std_logic_vector(1 downto 0);
        s00_axi_rvalid  : out std_logic;
        s00_axi_rready  : in std_logic
    );
end simoROM_v1_0;

architecture arch_imp of simoROM_v1_0 is

    -- component declaration
    component simoROM_v1_0_S00_AXI is
        generic (
        C_S_AXI_DATA_WIDTH  : integer   := 32;
        C_S_AXI_ADDR_WIDTH  : integer   := 4
        );
        port (
        S_AXI_ACLK  : in std_logic;
        S_AXI_ARESETN   : in std_logic;
        S_AXI_AWADDR    : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
        S_AXI_AWPROT    : in std_logic_vector(2 downto 0);
        S_AXI_AWVALID   : in std_logic;
        S_AXI_AWREADY   : out std_logic;
        S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
        S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
        S_AXI_WVALID    : in std_logic;
        S_AXI_WREADY    : out std_logic;
        S_AXI_BRESP : out std_logic_vector(1 downto 0);
        S_AXI_BVALID    : out std_logic;
        S_AXI_BREADY    : in std_logic;
        S_AXI_ARADDR    : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
        S_AXI_ARPROT    : in std_logic_vector(2 downto 0);
        S_AXI_ARVALID   : in std_logic;
        S_AXI_ARREADY   : out std_logic;
        S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
        S_AXI_RRESP : out std_logic_vector(1 downto 0);
        S_AXI_RVALID    : out std_logic;
        S_AXI_RREADY    : in std_logic
        );

    end component simoROM_v1_0_S00_AXI;

    -- ADDED BY SIMOZZ
    -- start simo custom block declaration
    -- declare 4 memory address each of 8 bit wide data type
    TYPE mymemory IS ARRAY (0 TO 7) OF STD_LOGIC_VECTOR (31 DOWNTO 0);
    CONSTANT myrom : mymemory := (
        0 => x"00000080" ,
        1 => x"00000040" ,
        2 => x"00000020" ,
        3 => x"00000010" ,
        4 => x"00000008" ,
        5 => x"00000004" ,
        6 => x"00000002" ,
        7 => x"00000001" 
    );
    -- end simo block declaration


begin

-- Instantiation of Axi Bus Interface S00_AXI
simoROM_v1_0_S00_AXI_inst : simoROM_v1_0_S00_AXI
    generic map (
        C_S_AXI_DATA_WIDTH  => C_S00_AXI_DATA_WIDTH,
        C_S_AXI_ADDR_WIDTH  => C_S00_AXI_ADDR_WIDTH
    )
    port map 
    (
        S_AXI_ACLK  => s00_axi_aclk,
        S_AXI_ARESETN   => s00_axi_aresetn,
        S_AXI_AWADDR    => s00_axi_awaddr,
        S_AXI_AWPROT    => s00_axi_awprot,
        S_AXI_AWVALID   => s00_axi_awvalid,
        S_AXI_AWREADY   => s00_axi_awready,
        S_AXI_WDATA => s00_axi_wdata,
        S_AXI_WSTRB => s00_axi_wstrb,
        S_AXI_WVALID    => s00_axi_wvalid,
        S_AXI_WREADY    => s00_axi_wready,
        S_AXI_BRESP => s00_axi_bresp,
        S_AXI_BVALID    => s00_axi_bvalid,
        S_AXI_BREADY    => s00_axi_bready,
        S_AXI_ARADDR    => s00_axi_araddr,
        S_AXI_ARPROT    => s00_axi_arprot,
        S_AXI_ARVALID   => s00_axi_arvalid,
        S_AXI_ARREADY   => s00_axi_arready,
        S_AXI_RDATA => s00_axi_rdata,
        S_AXI_RRESP => s00_axi_rresp,
        S_AXI_RVALID    => s00_axi_rvalid,
        S_AXI_RREADY    => s00_axi_rready
    );

    -- ADDED BY SIMOZZ
    -- Add user logic here
    -- start simo custom block
    PROCESS (s00_axi_aclk) BEGIN
       IF (s00_axi_aclk'Event AND s00_axi_aclk='1')
           s00_axi_rdata <= myrom (s00_axi_araddr);
       END IF;
    END PROCESS;
    -- end simo custom block
    -- User logic ends

end arch_imp;

 

 

The last block simo custom block is giving me another error:

 

[Synth 8-2778] type error near s00_axi_araddr ; expected type integer ["simoROM_v1_0.vhd":138]
[Synth 8-2715] syntax error near s00_axi_rdata ["simoROM_v1_0.vhd":138]
[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

 

Is Vivado telling me that I have to cast std_logic to integer ? If so,

 

I also have another question: given the two files generated by Vivado, in my case:

 

simoROM_v1_0.vhd

simoROM_v1_0_S00_AXI.vhd

 

which of them is convenient to customize ?

 

The first one has definitions of the pins.

The second one implements the standard behavior of my AXI slave component.

 

If you consider it's better to open another thread, I will.

 

Regards,

Simon

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Moderator
Moderator
3,219 Views
Registered: ‎11-09-2015

Re: Custom AXI IP - VHDL error code

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Hi @simozz,

 

The address of an array must be an integer:

    PROCESS (s00_axi_aclk) BEGIN
       IF (s00_axi_aclk'Event AND s00_axi_aclk='1')
           s00_axi_rdata <= myrom(to_integer(unsigned(s00_axi_araddr)));
       END IF;
    END PROCESS;

See AR#45213

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Explorer
Explorer
3,195 Views
Registered: ‎05-14-2017

Re: Custom AXI IP - VHDL error code

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Hello,

 

The first message pointed out the problem.

 

However, tha last block (of the last message) will not work.

I am struggling with that code  I am still not expert with data conversion.

 

IMPORTANT: the posted code will not work so don't keep it as a working example.

 

Regards,

Simon

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