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Explorer
Explorer
2,998 Views
Registered: ‎05-14-2017

Custom AXI creation : which VHDL should be modified ?

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Hello,

 

I have a question regarding the creation and customization of an AXI IP.

 

Suppose I create a slave AXI IP simoROM version 1.0. After that, Vivado creates two VHDL files:

 

simoROM_v1_0.vhd

simoROM_v1_0_S00_AXI.vhd

 

The first one has definitions of the pins only.

The second one implements the standard behavior of my AXI slave component.

 

Which of them should be customized to implement the behavior of my IP ?

I am a little bit confused.

 

Thank you.

Regards,

Simon

 

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Moderator
Moderator
5,363 Views
Registered: ‎11-09-2015

Re: Custom AXI creation : which VHDL should be modified ?

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Hi @simozz,

 

It depends on what you are doing. But you can modify both.

 

simoROM_v1_0_S00_AXI.vhd > would be things related to the interface S00

simoROM_v1_0.vhd > would be for general things

 

In you case, as you are doing a ROM, I would modify only simoROM_v1_0_S00_AXI.vhd as you only want to give values to addresses read through the interface.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Moderator
Moderator
5,364 Views
Registered: ‎11-09-2015

Re: Custom AXI creation : which VHDL should be modified ?

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Hi @simozz,

 

It depends on what you are doing. But you can modify both.

 

simoROM_v1_0_S00_AXI.vhd > would be things related to the interface S00

simoROM_v1_0.vhd > would be for general things

 

In you case, as you are doing a ROM, I would modify only simoROM_v1_0_S00_AXI.vhd as you only want to give values to addresses read through the interface.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Explorer
Explorer
2,986 Views
Registered: ‎05-14-2017

Re: Custom AXI creation : which VHDL should be modified ?

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Hello @florentw

 

Nice. Could you just make an example of what you mean for "general things" ?

I understand that I can customize SLAVE or MASTER behavior. But what else I can customize more than these ?

 

Thank you.

Regards,

Simon

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Moderator
Moderator
2,981 Views
Registered: ‎11-09-2015

Re: Custom AXI creation : which VHDL should be modified ?

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Hi @simozz,

 

Example on a very basic IP: and adder on a value coming from the input with one value from the register (programmed by the zynq).

 

I would manage the write to the register via the AXI interface in myIP_v1_0_S00_AXI.vhd and then do the adder operation in myIP_v1_0.vhd (as this is not related to the AXI interface).

 

Picture1.png

 

Does it make sense?

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Explorer
Explorer
2,977 Views
Registered: ‎05-14-2017

Re: Custom AXI creation : which VHDL should be modified ?

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Oh yes. Now it's clear !

 

Thank you.

Regards,

Simon

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Scholar ronnywebers
Scholar
476 Views
Registered: ‎10-10-2014

Re: Custom AXI creation : which VHDL should be modified ?

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@florentw

I've seen other tutorials where people just start coding their custom logic straight into the 'some_ip_s00_axi.vhd' file, also, there are comments at the bottom of this file 'insert custom code here'. But I never liked this.

Then I came acros great tutorial, and I started using this method for my custom AXI ip.

The guy who wrote this tutorial 'abstracts' the slv_reg0, slv_reg1, ... from the 'some_ip_s00_axi.vhd' template, and exposes these registers to the top-level file 'some_ip.vhd'.  He also 'separates' read and write, in case you want to implement a 'loopback register', you need to attach the read and write register in the top-level file. 

This way, there is no need to put any custom logic into the some_ip_s00_axi.vhd file (at the 'insert custom code here')

I used this method several times in custom AXI IP, and I did not regret it so far, but I'm wondering what your opinion is on this - is this a good method? how do you handle this? Do you put code in the some_ip_s00_axi.vhd file?

 

** kudo if the answer was helpful. Accept as solution if your question is answered **
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Custom AXI creation : which VHDL should be modified ?

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Hi @ronnywebers,

If you didn't have any error so far and you think it is simple, yes it seems to be a good method ;)

The generated RTL is only an example.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**