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dcwhitehead
Adventurer
Adventurer
4,604 Views
Registered: ‎03-28-2014

DDR4 MIG fails to synthesize with Vivado 2016.2

I'm generating the DDR4 MIG IP for a Kintex xcku085-flvb1760-1-c FPGA, but synthesis of the Out-Of-Context IP is failing without providing any useful information as to why. The memory is an SODIMM (MTA18ASF1G72HZ_2G1). The .xci file and synthesis reports are attached.

 

Any help with getting this to synthesize would be greatly appreciated.

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viviany
Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

How did you know "Synthesis is failing"? Was the Synthesis process halting (log didn't change for a very long time)? Did the GUI give any pop-up window indicating it failed (if yes, what did it say)? Did the GUI crash?

 

Here are something that you could try:

1. Try newer version of Vivado, e.g. 2016.4, 2017.1.

2. Try Global mode of MIG but not Out-Of-Context.

 

Thanks

Vivian

 

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dcwhitehead
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Registered: ‎03-28-2014

The Vivado GUI reports a synthesis design error, but there is no other indication of a problem (no crashes, log problems, infinite run time, etc.)  I will try running it as global then update versions of Vivado.

synth_error.png

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dcwhitehead
Adventurer
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Registered: ‎03-28-2014

Switching the IP from OOC to Global did not help, but I was able to get it to work by switching to Vivado 2017.1. When building in 2017.1, I initially got a warning/error about the file path being greater than 146 characters (it was 150 characters), so maybe this was the problem in 2016.2?

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viviany
Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

Very likely that this was the problem in 2016.2. And you can verify that by reducing the path to the project directory in 2016.2.

 

Thanks

Vivian

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dcwhitehead
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Registered: ‎03-28-2014

I just ran it again in 2016.2 with a shortened file path and the IP still fails to build, so it was something else.

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viviany
Xilinx Employee
Xilinx Employee
4,428 Views
Registered: ‎05-14-2008

I created a project in 2016.2 and added your .xci file in the project. When I right clicked on the .xci and selected "Generate Output Products", I received the following errors:

mig.png

 

I then changed the IP to Global mode and the IP could be generated without error. After that I changed the IP back to Out-of-Context mode and generated output products, everything worked well. The OOC Synthesis run completed successfully.

 

Not sure if your issue has anything to do with the errors I encountered.

Do you still need it to be run in 2016.2? Is moving to 2017.1 a good option for you?

 

Thanks

Vivian

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dcwhitehead
Adventurer
Adventurer
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Registered: ‎03-28-2014

That's interesting. The MIG IP was generated through 4DSP's Stellar IP tool as part of their example design, so I would think it would be valid. My current Vivado license only goes through 2016.2, but I have an eval license and we should be updating our license soon.

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floh
Newbie
Newbie
1,297 Views
Registered: ‎10-03-2017

I had the same problem with Vivado 2016.2. For me the solution was to use a shorter path for working directory.

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