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athwaz
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Registered: ‎07-09-2018

DRC errors in Synthesis

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I am trying to synthesize my MAC module with BUF_GT inserted in the design and adding the constraints for the MAC ports to use GTHE location, but I am getting below error.

Can you please help me understand below errors

ERROR: [DRC NSTD-1] Unspecified I/O Standard: 8 out of 95 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.

ERROR: [DRC REQP-1871] BUFG_GT_pins_CE_CLR_not_driven_by_BUFG_GT_SYNC: BUFG_GT top_inst/g_bufg_rx[0].m_bufg_rx CE pin should be driven by an inserted BUFG_GT_SYNC, but is not. Check for DONT_TOUCH on the BUFG_GT or the instantiated module that contains the BUFG_GT which prevents BUFG_GT_SYNC insertion. Resolution: Remove the DONT_TOUCH constraint or explicitly instantiate a BUFG_GT_SYNC and connect it to drive the CE and CLR pins of the BUFG_GT.

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anusheel
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Registered: ‎07-21-2014

@athwaz

 

The IO standard related DRC is generally from write_bitstream/implementation phase:

https://www.xilinx.com/support/answers/56354.html

 

The real error I see from the synthesis side is ERROR: [DRC REQP-1871]  which talks about connection. Please correct the connection as mentioned in error. Also, if you need more help on GT related connections, please post your query on https://forums.xilinx.com/t5/Serial-Transceivers/bd-p/transceivers

 

Thanks

Anusheel 

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prathikm
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Registered: ‎09-15-2016

Hi @athwaz,

 

I guess the DRC NSTD-1 is stating the IO standards as not defined by user. You can open the schematic and on the right top, go to 'I/O Planning' view and see at the bottom of screen in I/O ports column > I/O Std and change as needed.

 

The BUFG_GT_SYNC is synchronizer circuit for BUFG_GTs. Not sure why it is not inserted by tool, but as message says it should be there. UG572 (page.no.32) I suggest you can check the schematic and code to debug it.

 

Thanks

Prathik

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anusheel
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Registered: ‎07-21-2014

@athwaz

 

The IO standard related DRC is generally from write_bitstream/implementation phase:

https://www.xilinx.com/support/answers/56354.html

 

The real error I see from the synthesis side is ERROR: [DRC REQP-1871]  which talks about connection. Please correct the connection as mentioned in error. Also, if you need more help on GT related connections, please post your query on https://forums.xilinx.com/t5/Serial-Transceivers/bd-p/transceivers

 

Thanks

Anusheel 

View solution in original post

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