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Explorer
Explorer
8,981 Views
Registered: ‎10-25-2011

Debugging RTL for "unconnected registers"

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I'm getting several "...is unconnected and will be removed" warnings in Vivado (2015.4). I am aware that this is almost always a problem with the RTL and I've successfully debugged my RTL in the past when faced with these warnings. However, this time I am stumped. I have traced a path all the way from the data coming into our IP (we're using a Zynq, so over the AXIS HP ports) to it leaving the IP (also over the HP port).

 

The IP works fine in simulation - it produces meaningful, non-zero data. The inputs and outputs work - I have HP0 connected to the IP and HP1 simply doing a loopback; HP1 data correctly loops back. Given that, I have no idea how to debug this. Is there any way to figure out what triggered Vivado to start removing registers (i.e., which of the regs it removed was the first)?

 

 

 

Finally, I have a message I have never seen before - 

WARNING: [Synth 8-3936] Found unconnected internal register 'offset_reg' and it is trimmed from '23' to '16' bits.

Does this mean that the entire register is unconnected or that only the bits being trimmed are unconnected? This message appears in the "RTL Optimization" phase (Phase 2), much before the "cross boundary optimization" phase which is where a slew of other "unconected" warnings appear. Can I assume the above message triggered the others?

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Xilinx Employee
Xilinx Employee
16,150 Views
Registered: ‎05-20-2015

Re: Debugging RTL for "unconnected registers"

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Hi @vgokhale,

Here's the sample usage of the attribute.

module dont_touch(input in1,input in2,input in3,input in4,output out1,output out2);

(* dont_touch = "true" *) wire sig1; 
assign sig1 = in1 & in2;
assign out1 = sig1 & in2;

(* dont_touch = "false" *) wire sig2;
assign sig2 = in3 & in4;
assign out2 = sig2 & in4;
endmodule

 

Thanks,

Rajesh

 

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4 Replies
Moderator
Moderator
8,979 Views
Registered: ‎01-16-2013

Re: Debugging RTL for "unconnected registers"

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@vgokhale,

 

I think that the bits from 16 to 23 are always unused so the tool must be trimming them. 

Just to debug can you try applying dont_touch attribute on this signal:

 

attribute dont_touch : string;
attribute dont_touch of <signal_name> : signal is "true";

 

Check page number 41 in below synthesis user guide for more details:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug901-vivado-synthesis.pdf

 

--Syed

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Explorer
Explorer
8,943 Views
Registered: ‎10-25-2011

Re: Debugging RTL for "unconnected registers"

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I am using verilog so I used the verilog version of the attribute syntax you showed ((* DONT_TOUCH = “yes” *)) and for all three versions (wire attribute, module attribute and instance attribute), Vivado gave my a syntax error on the line that I had the attribute.

 

Am I missing something in the syntax?

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Xilinx Employee
Xilinx Employee
16,151 Views
Registered: ‎05-20-2015

Re: Debugging RTL for "unconnected registers"

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Hi @vgokhale,

Here's the sample usage of the attribute.

module dont_touch(input in1,input in2,input in3,input in4,output out1,output out2);

(* dont_touch = "true" *) wire sig1; 
assign sig1 = in1 & in2;
assign out1 = sig1 & in2;

(* dont_touch = "false" *) wire sig2;
assign sig2 = in3 & in4;
assign out2 = sig2 & in4;
endmodule

 

Thanks,

Rajesh

 

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Explorer
Explorer
7,996 Views
Registered: ‎10-25-2011

Re: Debugging RTL for "unconnected registers"

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I'm accepting the above as the solution because it worked in preventing the signals in the module from being removed. However, it (obviously) did not fix the bug in my RTL. Unfortunately, without more information on what triggered the signals to be removed was taking far too long. Instead, I re-wrote the module under question differently and I suppose somewhere along the way I fixed my own bug. Thank you for your help with this.

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