06-09-2017 05:52 AM
I am synthesising AES encryption algorithm on Virtex-7.
There is something happened, and I would like to understand why it happened that way.
There's a part of the AES called the s-box, which a prescribed values, used to give make a byte substitution, and by that I mean, the s-box takes a byte (call it b0) , looks for the associated value (call it b1) to this byte, and then replace b0 with b1.
I got a design, where this s-box is implemented using ARRAY (0 to 255) of STD_LOGIC_VECTOR(7 downto 0).
I have made some modifications to this part, thus, the s-box now implemented using with.. select statement, which depends as follows
with b0= xxxxxxxx, select b1=yyyyyyyy.
and I used this instead of the array in the design.
In both scenarios, the s-box is synthesised as a LUT, however, this caused a significant power reduction.
Why did this power reduction happen, in spite of the fact the s-box in both cases is synthesised as a LUT?
I am using Vivado 2015.4. and VHDL.
06-09-2017 07:40 AM
Open the implemented design, and look at it,
06-09-2017 07:42 AM
06-09-2017 08:16 AM
Or look at the usage report.
How many LUT and of what type? (LUT2, LUT3, LUT4, LUT5, LUT6)
Coding style makes a difference. Some styles are more resource efficient, some are more power efficient.
How many levels of logic are there between registers? (pipelining) The more pipelined a design is, the faster it can go. The faster the clock, the higher the dynamic power.