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Registered: ‎08-10-2016

Disable signal optimization doesn't work in XST

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I want to use two signals in order to create a probe with FPGA editor. I have my code in vhdl:

 

attribute keep: string;

--Some code here

signal within_crc :std_logic := '0';--! FOR TEST ONLY!!
signal within_state : std_logic := '0'; --! FOR TEST ONLY!!
  
attribute keep of within_crc: signal is "true";
attribute keep of within_state : signal is "true";

But it seems that XST ignore or change their name, and I'm not able to find their nets in FPGA Editor. I looked over the synthesis report, and I only found the following messages relative to the signals:

 

Set property "KEEP = TRUE" for signal <within_crc>.
Set property "KEEP = TRUE" for signal <within_state>.

I don't know where can be the issue... 

 

Thanks,

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Moderator
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7,567 Views
Registered: ‎07-21-2014

Re: Disable signal optimization doesn't work in XST

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fdomingues@ulmaembedded.com

 

Use Save(S) attribute to prevent the nets in synthesis and implementation phases.

Check below links for more details:

https://www.xilinx.com/support/answers/35504.html

https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst.pdf

 

Thanks,
Anusheel
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1 Reply
Highlighted
Moderator
Moderator
7,568 Views
Registered: ‎07-21-2014

Re: Disable signal optimization doesn't work in XST

Jump to solution

fdomingues@ulmaembedded.com

 

Use Save(S) attribute to prevent the nets in synthesis and implementation phases.

Check below links for more details:

https://www.xilinx.com/support/answers/35504.html

https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst.pdf

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

View solution in original post