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Registered: ‎05-21-2009

Discrepencies between behavioral simulation and implementation in verilog

Hi,

 

I lost 2 days on this problem, now that I found the solution I would like to share  and may be understand if someone knows

 

This verilog was working nice in behavioral simulation but not in implementation

 

reg [31:0]         ads_reg[0:20];
wire  [4:0]        addr;
wire              
ads_sign;


assign             ads_sign = ads_reg[
addr][31];

 

 

This modification is working in implementation

 

 

reg [31:0]         ads_reg[0:20];
wire  [4:0]        addr;
wire  [31:0]       ads_data;

wire               ads_sign;


assign             ads_data = ads_reg[addr];

assign             ads_sign = ads_data[31];

 

 

Similarily this was working nice in behavioral simulation but not in implementation

reg [31:0]         ads_reg[0:20];
reg [31:0]         data;
wire  [4:0]        addr;
wire              
ads_sign;

 

always @(posedge clock_proc)
   begin :

   ads_reg[addr][31]<=data[31] ;

   end

 Actually this line ads_reg[addr][31]<=data[31] ; was just like removed! info warning was:

 Xst:2679 - Register <ads_reg<0..21><31>> in unit <motor_regblock> has a constant value of 0 during circuit operation. The register is replaced by logic.

 

This modification is working in implementation (ok not funktionnaly the same but was ok in my application)

 

 

reg [31:0]         ads_reg[0:20];
reg [31:0]         data;
wire  [4:0]        addr;
wire              
ads_sign;

 

always @(posedge clock_proc)
   begin :

   ads_reg[addr]<=data;

   end

 

 

 Hope this helps!

 

Marcel

 

Message Edited by mguw on 08-17-2009 02:48 AM
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