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Visitor
316 Views
Registered: ‎09-19-2018

## Divide std_logic_vector by constant with fractional part

Hi guys, ive been messing around these last days trying to implement these simple 4 equations in my Nexys 4 FPGA:

--p[n] = (m1[n]+m2[n]+m3[n]+m4[n])*0.25

--ux[n] = (m2[n]-m1[n])/30.7

--ux[n] = (m4[n]-m3[n])/30.7

--uz[n] = (m4[n]+m3[n]-m1[n]-m2[n])/(43.4163)

where all X[n] signals are signed 18 bit numbers, and the maximum size of bits i can use in my project for the std_logic_vectors is 32

I have tried doing this with the fixed_pkg library but i dont know if this is the correct way to do that, can someone give me some advice or any tip to do this ?

Thank you all!!

2 Replies
Scholar
250 Views
Registered: ‎08-01-2012

## Re: Divide std_logic_vector by constant with fractional part

Why are you limited to 32 bits?

Fixed pkg will work. But you wont get any pipelining and FMax will be poor if you want to divide. You should generate a divider IP core to do it.

Scholar
239 Views
Registered: ‎07-09-2009

## Re: Divide std_logic_vector by constant with fractional part

Ah dividing in digits.

Don't ....

As these are constants , multiply by the reciprical ..

called magic numbers. this might give you an idea.

https://surf-vhdl.com/how-to-implement-division-in-vhdl/

look up the book 'hackers delight'

And have a look through these guys, https://www.dsprelated.com/forums

look for Q notation also.

https://en.wikipedia.org/wiki/Q_%28number_format%29