09-24-2020 03:13 AM
The UG901 states that division is "Supported only if the second operand is a power of 2, or both operands are constant." What does it actually mean? Are we talking about integers, std_logic_vector, unsigned, signed, sfixed, ufixed etc.?
I tried implementing a division like:
a <= b/c;
where both the divisor and dividend are of sfixed type and that actually works even if it creates tons of logic. If I'm right, the above division uses the divide function in the fixed_generic_pkg package, which in turn uses or ends up in the DIVMOD procedure in the numeric_std package. And what is actually the purpose of this procedure? Is it really meant to be used for synthesis? Or only simulation?
09-03-2021 01:52 AM
The answer is that Xilinx have chosen not to support synthesising it, because a single clock version of a divide that is not a power of two will likely given a very slow design. And hence you need to use the divide IP core, which cannot (currently) be inferred by the divide function.
Other manufacturers do allow it (Intel) but like with Xilinx, you dont get a very good divide solution.
So your options are:
1. Manually Place a divide IP core and connect.
2. Redesign your algorithm to use a 1/N multiply rather than divide. This can be completed in a single clock very effeciently.
09-03-2021 02:35 AM
It was almost a year ago since i originally asked the question, but I seem to recall that the division actually got implemented. However, it created tons of logic and wasn't really useable. I never intended to implement the division like that, it was more out of curiosity i tried it out. Whenever I need a division, I use the Divider Generator. Too bad, however, that you can't use generics to configure it.
09-03-2021 11:17 AM
From the looks of it, DIVMOD() appears to be synthesizable, also looks resource intensive with comparisons and subtractions inside of a loop. As to the statement "Supported only if the second operand is a power of 2, or both operands are constant." , well if that's the case, then no actual division (in hardware) needs to be done, it's either a shift, of a compile-time division (and rounding or truncation - I don't remember).
So, divisions by powers of 2 are great, other than that try to get to a power of 2 by first doing a subtraction (or possible counting the number of repeated subtractions - if you can afford the number of clock cycles it can take). Other than that, use the core generator.