06-21-2013 05:41 AM
Hello everyone,
I have always used RTL design method until now; however currently I need to make use of recursion since the "network" that I am trying to implement is a bit complicated.
Anyways, I handled most of the problems, and simulation seems to be working fine. Despite some bit assignment warnings in the synthesis, I get the warning message "More than 100% of Device resources are used" and ofc the synthesis stops.
I attached my code below. It would be real great if anyone could help me.
By the way I am using Virtex 5 XC5VLX50 and package FF324. And I have Xilinx ISE Webpack.
06-22-2013 08:08 AM
06-21-2013 07:20 AM
Well, which of the resources are over-used? I would guess the IO pins, in which case: Don't worry, this would go away in a complete design.
Also, don't do this:
module A(x);
input x;
Instead, do this:
module A(input x);
06-21-2013 08:42 AM
Well, at the error message I am not given info on which specific part of the devic is tried to be overused. The message is exactly like that:
"(*) More than 100% of Device resources are used"
and I guess I cannot view the rest of the possible synthesis errors/warnings since I get this warning, because the synthesis tool instantly stops.
This could be a serious problem or is it certain that I can remove it when I add different modules?
Thanks a lot for the reply by the way.
06-21-2013 09:44 AM
Please post the complete synthesis report. If that is not possible, post the synthesis log.
06-22-2013 07:36 AM
06-22-2013 08:08 AM
06-22-2013 10:48 AM
Thank you so much!