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Visitor manili
Visitor
3,494 Views
Registered: ‎12-27-2016

Does Vivado Synthesis tool, add signals to sensitivity list automatically ?

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Hi all,

Please take a look at below code :

 

module Test( input i );

     

     (* MARK_DEBUG = "TRUE" *) reg b;

     

     always @(i)

     begin

          if(i)

               b = 1'h0;

          else

               b = ~b;

     end

endmodule

 

After synthesizing this code I get the following result during Post-Synthesis-Simulation process with ModelSim simulator :

# ** Error (suppressible): (vsim-3601) Iteration limit 10000000 reached at time 20 ns.

But I have no problem with Behavioral-Simulation phase.

 

It seems that the Vivado adds "b" signal to the sensitivity list automatically, Isn't it ?

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Historian
Historian
6,690 Views
Registered: ‎01-23-2009

Re: Does Vivado Synthesis tool, add signals to sensitivity list automatically ?

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The short answer is "yes".

 

The longer answer is "what do you expect it to do?"

 

Synthesis is converting your RTL code into a netlist of interconnected cells. In FPGAs (and other digital logic), you have flip-flops, latches and combinatorial logic - that's it.

 

Interpreted literally (where b is not part of the sensitivity list), what hardware do you expect can implement what you have described? It would sort of look like a dual edged toggle flip-flop with a clear (or something like that). No such thing exists in an FPGA (or ASIC) - there are no dual-edge flip-flops (other than IDDRs and ODDRs which cannot be inferred this way).

 

So the tool has several choices - simply say "Error - what you have here cannot be synthesized" (since it can't), or assume you made a simple typographical error. It does the latter, and puts a warning in the synthesis log file to tell you that it has done so.

 

So now it needs to figure out what you meant. For always blocks, there are only two forms that are synthesizable

 

always @(posedge <clk>)

begin

   d <= ...

end

 

which infers a flip-flop. Note the posedge is required. Since your code does not have the posedge, it assumes it is not a flop.

 

The only other form that is legal is

 

always @(*)

begin

   ...

end

 

which, depending on what is between the begin and end is either combinatorial logic or a latch. In this case, it assumes full sensitivity in the always block, since both combinatorial logic and latches require full sensitivity.

 

The tool assumes your code is this form, and then goes on to create the combinatorial logic that has the b = ~b feedback, which is a combinatorial loop (literally a NAND gate with its output connected back to its input).

 

When you try and simulate this and i goes to a 1, the loop starts oscillating, and, in a zero time simulation, time stops (causing the iteration limit).

 

Avrum

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Highlighted
Historian
Historian
6,691 Views
Registered: ‎01-23-2009

Re: Does Vivado Synthesis tool, add signals to sensitivity list automatically ?

Jump to solution

The short answer is "yes".

 

The longer answer is "what do you expect it to do?"

 

Synthesis is converting your RTL code into a netlist of interconnected cells. In FPGAs (and other digital logic), you have flip-flops, latches and combinatorial logic - that's it.

 

Interpreted literally (where b is not part of the sensitivity list), what hardware do you expect can implement what you have described? It would sort of look like a dual edged toggle flip-flop with a clear (or something like that). No such thing exists in an FPGA (or ASIC) - there are no dual-edge flip-flops (other than IDDRs and ODDRs which cannot be inferred this way).

 

So the tool has several choices - simply say "Error - what you have here cannot be synthesized" (since it can't), or assume you made a simple typographical error. It does the latter, and puts a warning in the synthesis log file to tell you that it has done so.

 

So now it needs to figure out what you meant. For always blocks, there are only two forms that are synthesizable

 

always @(posedge <clk>)

begin

   d <= ...

end

 

which infers a flip-flop. Note the posedge is required. Since your code does not have the posedge, it assumes it is not a flop.

 

The only other form that is legal is

 

always @(*)

begin

   ...

end

 

which, depending on what is between the begin and end is either combinatorial logic or a latch. In this case, it assumes full sensitivity in the always block, since both combinatorial logic and latches require full sensitivity.

 

The tool assumes your code is this form, and then goes on to create the combinatorial logic that has the b = ~b feedback, which is a combinatorial loop (literally a NAND gate with its output connected back to its input).

 

When you try and simulate this and i goes to a 1, the loop starts oscillating, and, in a zero time simulation, time stops (causing the iteration limit).

 

Avrum

Tags (1)