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Scholar helmutforren
Scholar
2,758 Views
Registered: ‎06-23-2014

Does Vivado support SystemVerilog Verilog Unions?

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Darn.  I have a whole system working using SystemVerilog structures and unions.  Then, before Christmas break, I found that Vivado isn't supposed to support unions at all.  Therefore, my working system is on very thin ice.

 

I found Answer Record at https://www.xilinx.com/support/answers/55135.html .  However, I remember an actual PDF somewhere that said this, but I can't find it again.  QUESTION: Where was the PDF that said this?

 

Then, I'm wondering if 2017.4 officially DOES support unions, or at least more than the limited list in the AR implies.  I'd like to get off the thin ice, but I don't want to move from one set of thin ice to another set of thin ice, and fall through.  (That is, what manages to work today, with a few workarounds I had to put in, might not work at all in 2017.2,.3, or .4.  It's a complex system, and finding -- or not discovering -- deeply buried bugs from something like this is way too scary.

 

Thanks,

Helmut

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Moderator
Moderator
3,857 Views
Registered: ‎06-05-2013

Re: Does Vivado support SystemVerilog Verilog Unions?

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I can see in 2017.4 user guide that vivado synthesis does not support unions. check page#259
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug901-vivado-synthesis.pdf
Thanks
HJ
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Moderator
Moderator
3,858 Views
Registered: ‎06-05-2013

Re: Does Vivado support SystemVerilog Verilog Unions?

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I can see in 2017.4 user guide that vivado synthesis does not support unions. check page#259
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug901-vivado-synthesis.pdf
Thanks
HJ
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Scholar helmutforren
Scholar
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Registered: ‎06-23-2014

Re: Does Vivado support SystemVerilog Verilog Unions?

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Thanks.  So the answer is "UG901".  The 2017.1 UG901 is where I saw it.  Now it's documented to be easily found again in my forum posts, and the answer about 2017.4 is given.

Visitor amol_aeva
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Registered: ‎01-23-2018

Re: Does Vivado support SystemVerilog Verilog Unions?

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Vivado Synthesis doesn't support Unions but they should work in Simulation. See UG900 for that. So if they are only used in your testbench you should be ok.

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Scholar helmutforren
Scholar
2,724 Views
Registered: ‎06-23-2014

Re: Does Vivado support SystemVerilog Verilog Unions?

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Note I have them actually RUNNING on the FPGA hardware, with 90% success and 10% workaround.  So they ARE in fact PARTIALLY and POORLY supported, as opposed to not supported at all.  This is certainly true for 2017.1.  My associate builds with 2017.2 and it might also be the same.  Anyway, this underlies my fear of upgrading.

Scholar markcurry
Scholar
2,716 Views
Registered: ‎09-16-2009

Re: Does Vivado support SystemVerilog Verilog Unions?

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That's VERY bad behavior by Vivado.  If it's not supported (as UG901 indicated) it should error out.  Producing logic which doesn't match the RTL description is absolutely the worst thing the tool could do.

 

Xilinx should fix Vivado to either (a) error out on Unions, or (b) complete the support and make it officially supported.

 

Regards.

 

Mark

Scholar helmutforren
Scholar
2,711 Views
Registered: ‎06-23-2014

Re: Does Vivado support SystemVerilog Verilog Unions?

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LOL. I agree completely. I already had a huge investment in working code, then posted about bugs, then worked around, then posted about more bugs, then worked around, then discovered it wasn't supported. I won't hold my breath for Xilinx to get around to what you suggest. (Frankly, I don't see why it's so hard. I have already envisioned future rewrites of this code, to implement what is in essence unions by defining the structs separately and using knowledgeable code to copy from one var to another in order to accomplish the desired result. I would think Synth could do exactly that under the covers. Note I'm thinking of packed unions and structures.)
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Xilinx Employee
Xilinx Employee
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Registered: ‎01-11-2011

Re: Does Vivado support SystemVerilog Verilog Unions?

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I agree that we should give an error instead of providing wrong logic for this. Is there an example that you can provide that shows this so I can report it to development to address?

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