01-24-2018 12:10 PM
Darn. I have a whole system working using SystemVerilog structures and unions. Then, before Christmas break, I found that Vivado isn't supposed to support unions at all. Therefore, my working system is on very thin ice.
I found Answer Record at https://www.xilinx.com/support/answers/55135.html . However, I remember an actual PDF somewhere that said this, but I can't find it again. QUESTION: Where was the PDF that said this?
Then, I'm wondering if 2017.4 officially DOES support unions, or at least more than the limited list in the AR implies. I'd like to get off the thin ice, but I don't want to move from one set of thin ice to another set of thin ice, and fall through. (That is, what manages to work today, with a few workarounds I had to put in, might not work at all in 2017.2,.3, or .4. It's a complex system, and finding -- or not discovering -- deeply buried bugs from something like this is way too scary.
01-24-2018 12:19 PM
01-24-2018 12:19 PM
01-24-2018 12:39 PM
Thanks. So the answer is "UG901". The 2017.1 UG901 is where I saw it. Now it's documented to be easily found again in my forum posts, and the answer about 2017.4 is given.
01-24-2018 01:25 PM - edited 01-24-2018 01:26 PM
Vivado Synthesis doesn't support Unions but they should work in Simulation. See UG900 for that. So if they are only used in your testbench you should be ok.
01-24-2018 01:36 PM
Note I have them actually RUNNING on the FPGA hardware, with 90% success and 10% workaround. So they ARE in fact PARTIALLY and POORLY supported, as opposed to not supported at all. This is certainly true for 2017.1. My associate builds with 2017.2 and it might also be the same. Anyway, this underlies my fear of upgrading.
01-24-2018 01:49 PM
That's VERY bad behavior by Vivado. If it's not supported (as UG901 indicated) it should error out. Producing logic which doesn't match the RTL description is absolutely the worst thing the tool could do.
Xilinx should fix Vivado to either (a) error out on Unions, or (b) complete the support and make it officially supported.
01-24-2018 02:08 PM
01-25-2018 09:27 AM
I agree that we should give an error instead of providing wrong logic for this. Is there an example that you can provide that shows this so I can report it to development to address?