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Explorer
Explorer
601 Views
Registered: ‎09-13-2011

Double invert issue 2017.4

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In an axi port expander using VHDL inout port records I was trying to reduce warnings when I came across this.

 

I added a dummy signal as an inverted copy of original signal and distributed inverted copies of this signal to inout-ports to avoid the multi-driven nets critical warning. It seems to work, the critical warning from synthesis is gone, but looking at the elaborated design the result looks wrong. Second line of inverters are missing. I haven't tried the final implementation if that works but it doesn't add to the confidence of the tool output.

 

    dummy_bready    <= not s_axilite.bready;
    dummy_rready    <= not s_axilite.rready;
    
    -- Distribution of non-retimed broadcast signals
    g_broadcast : for i in 0 to C_NO_MASTER_PORTS-1 generate
        m_axilite_i(i).bready <= not dummy_bready;
        m_axilite_i(i).rready <= not dummy_rready;
    end generate;

Doubble_invert_missing.png

 

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1 Solution

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Explorer
Explorer
305 Views
Registered: ‎09-13-2011

Re: Double invert issue 2017.4

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It has been awhile. 2017.4 seems to have trouble with using records so this was an attempt to get rid of some warnings (can't remember exactly what warnings). Adding the double invertering shouldn't make any difference, however the schematic showed only one level of inverters. That was the issue. I haven't tried it in later versions. We fixed the issue in our code by added a forcing of 'Z' onto the signals instead. Not sure why this helped but it did. Haven't had time to investigate fully.

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2 Replies
Teacher xilinxacct
Teacher
395 Views
Registered: ‎10-23-2018

Re: Double invert issue 2017.4

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@tsjorgensen

It looks a bit odd to me (assuming the is no code left out)...

Do you really mean to do continuous assignments into the dummies and the real values? (or should the dummies be local variables)

Hope that helps

If so, please mark as 'solution accepted'

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Explorer
Explorer
306 Views
Registered: ‎09-13-2011

Re: Double invert issue 2017.4

Jump to solution

It has been awhile. 2017.4 seems to have trouble with using records so this was an attempt to get rid of some warnings (can't remember exactly what warnings). Adding the double invertering shouldn't make any difference, however the schematic showed only one level of inverters. That was the issue. I haven't tried it in later versions. We fixed the issue in our code by added a forcing of 'Z' onto the signals instead. Not sure why this helped but it did. Haven't had time to investigate fully.

0 Kudos