03-24-2011 07:00 AM
I've created a new project in ISE Project Navigator 13.1, included testbench and all files in the project. My module is set as the Top module. When I click "Implement Top Module", all I get is an error
ERROR:Xst:2369 - Empty project file "T:\xilinx\workspace\Viterbi\Viterbi.prj"
That file is actually empty. How can I populate the file? Deleting it does nothing, and restarting Project Navigator gets me nowhere.
03-28-2011 08:22 AM
Have you observes that the design hierarchy is correctly built?
04-22-2011 03:45 PM
The project file would list all of the VHDL/Verilog sources that would be used for synthesis/implementation. Did you try running some example design? Maybe that will give you some insight on the flow.