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Newbie
Newbie
5,501 Views
Registered: ‎03-24-2011

ERROR: Empty Project file

I've created a new project in ISE Project Navigator 13.1, included testbench and all files in the project. My module is set as the Top module. When I click "Implement Top Module", all I get is an error

 

ERROR:Xst:2369 - Empty project file "T:\xilinx\workspace\Viterbi\Viterbi.prj"

 

That file is actually empty. How can I populate the file? Deleting it does nothing, and restarting Project Navigator gets me nowhere.

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Xilinx Employee
Xilinx Employee
5,457 Views
Registered: ‎03-24-2010

Re: ERROR: Empty Project file

Have you observes that the design hierarchy is correctly built?

Regards,
brucey
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Participant
Participant
5,310 Views
Registered: ‎05-11-2010

Re: ERROR: Empty Project file

The project file would list all of the VHDL/Verilog sources that would be used for synthesis/implementation. Did you try running some example design? Maybe that will give you some insight on the flow.

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