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Registered: ‎10-09-2013

ERROR:HDLCompilers:26 - expecting '=', found '[

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i am making a database for my program. the idea is to fetch the required paramenter and then use is it in the next process. the code has been given. can anyone please help me remove the error :(

 

module database( out1, a );
input [0:3]a;
output reg out1;
reg [0:9]x;

parameter x[0]=8'b00000000;
parameter x[1]=8'b00000001;
parameter x[2]=8'b00000010;
parameter x[3]=8'b00000011;
parameter x[4]=8'b00000100;
parameter x[5]=8'b00000101;
parameter x[6]=8'b00000110;
parameter x[7]=8'b00000111;
parameter x[8]=8'b00001000;
parameter x[9]=8'b00001001;

always@(*)
case (a)

4'd0 : out1=x[0];
4'd1 : out1=x[1];
4'd2 : out1=x[2];
4'd3 : out1=x[3];
4'd4 : out1=x[4];
4'd5 : out1=x[5];
4'd6 : out1=x[6];
4'd7 : out1=x[7];
4'd8 : out1=x[8];
4'd9 : out1=x[9];
default: $display("invailid");
endcase
endmodule

 

error:

ERROR:HDLCompilers:26 - "database.v" line 27 expecting '=', found '['
ERROR:HDLCompilers:26 - "database.v" line 28 expecting '=', found '['
ERROR:HDLCompilers:26 - "database.v" line 29 expecting '=', found '['
ERROR:HDLCompilers:26 - "database.v" line 30 expecting '=', found '['
ERROR:HDLCompilers:26 - "database.v" line 31 expecting '=', found '['
ERROR:HDLCompilers:26 - "database.v" line 32 expecting '=', found '['
ERROR:HDLCompilers:26 - "database.v" line 33 expecting '=', found '['
ERROR:HDLCompilers:26 - "database.v" line 34 expecting '=', found '['
ERROR:HDLCompilers:26 - "database.v" line 35 expecting '=', found '['
ERROR:HDLCompilers:26 - "database.v" line 36 expecting '=', found '['

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Professor
Professor
8,571 Views
Registered: ‎08-14-2007

Re: ERROR:HDLCompilers:26 - expecting '=', found '[

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In addition to previous comments, "x" cannot be both a register and a parameter.  And even if you had a parameter, it can't be declared the way you do it with array subscripts.  That's where you get the syntax error.  If you wanted to have an array of 8-bit data initialized to some value, you could use an initial block to do it.  In fact in your case it could easily be done in a loop like:

 

reg [7:0] x [0:9];  // Ten 8-bit regs

integer i;

initial begin

  // Loop to initialize the array value to equal the subscript

  for (i = 0;i < 10;i = i + 1) x[i] = i;  // Don't worry that a 32-bit integer won't fit in an 8-bit vector, this is Verilog - not VHDL

end

 

You could also initialize the array to any set of 10 8-bit numbers, but that wouldn't use a loop.  For example:

 

initial begin

  x[0]=8'b00000000;
  x[1]=8'b00000001;
  x[2]=8'b00000010;
  x[3]=8'b00000011;
  x[4]=8'b00000100;
  x[5]=8'b00000101;
  x[6]=8'b00000110;
  x[7]=8'b00000111;
  x[8]=8'b00001000;
  x[9]=8'b00001001;
end

 

One other point.  If this is eventually intended for synthesis, you should place an assignment for out1 in the default case to avoid a latch.  The $display can stay there for synthesis, it will just be ignored.  If you don't care what value x takes in the default case, you can assign it to 8'bX and that allows the synthesizer to pick any convenient value.

 

A comment on style.  This is NOT VHDL.  You do NOT need leading zeroes in your constants (but you may place them there if it helps you visualize something).  You do NOT need to use binary to describe a constant regardless of the number of bits.  Your constant does NOT need to be sized to the variable you're assigning it to.  For example:

 

x[3] = 3;

x[3] = 8'b11;

x[3] = 8'd3;

x[3] = 8'h3;

 

are all equivalent.  Use the syntax that helps you see the purpose of the code.

 

Also Verilog 2001 came out a long time ago.  I'd suggest getting used to using the newer module port syntax:

 

module database

 (

    input wire [3:0] a,

    output reg [7:0] out1;

 );

 

This allows you to define the ports with their attributes on a single line, making it easier if you need to make changes, and making it easier to go back and quickly see what this module does.

 

Good luck.

-- Gabor

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Teacher
Teacher
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Registered: ‎03-31-2012

Re: ERROR:HDLCompilers:26 - expecting '=', found '[

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I am not sure if you realize that the binary representation of 9 is 1001. So if your code did what it supposed to do, it would generate 9 when it is given 9 (just to pick a number).

Now the actual issues with the code: out1 is only 1 bit wide. Assigning anything wider to it is useless.
reg [0:9] x declares x to be 1 thing of 10 bits wide. You seem to think it's going to be 10 things of 8 bits wide.
If you want to initialize x, you need to use an "initial" statement. If you want parameters you don't need the reg declaration.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Highlighted
Professor
Professor
8,572 Views
Registered: ‎08-14-2007

Re: ERROR:HDLCompilers:26 - expecting '=', found '[

Jump to solution

In addition to previous comments, "x" cannot be both a register and a parameter.  And even if you had a parameter, it can't be declared the way you do it with array subscripts.  That's where you get the syntax error.  If you wanted to have an array of 8-bit data initialized to some value, you could use an initial block to do it.  In fact in your case it could easily be done in a loop like:

 

reg [7:0] x [0:9];  // Ten 8-bit regs

integer i;

initial begin

  // Loop to initialize the array value to equal the subscript

  for (i = 0;i < 10;i = i + 1) x[i] = i;  // Don't worry that a 32-bit integer won't fit in an 8-bit vector, this is Verilog - not VHDL

end

 

You could also initialize the array to any set of 10 8-bit numbers, but that wouldn't use a loop.  For example:

 

initial begin

  x[0]=8'b00000000;
  x[1]=8'b00000001;
  x[2]=8'b00000010;
  x[3]=8'b00000011;
  x[4]=8'b00000100;
  x[5]=8'b00000101;
  x[6]=8'b00000110;
  x[7]=8'b00000111;
  x[8]=8'b00001000;
  x[9]=8'b00001001;
end

 

One other point.  If this is eventually intended for synthesis, you should place an assignment for out1 in the default case to avoid a latch.  The $display can stay there for synthesis, it will just be ignored.  If you don't care what value x takes in the default case, you can assign it to 8'bX and that allows the synthesizer to pick any convenient value.

 

A comment on style.  This is NOT VHDL.  You do NOT need leading zeroes in your constants (but you may place them there if it helps you visualize something).  You do NOT need to use binary to describe a constant regardless of the number of bits.  Your constant does NOT need to be sized to the variable you're assigning it to.  For example:

 

x[3] = 3;

x[3] = 8'b11;

x[3] = 8'd3;

x[3] = 8'h3;

 

are all equivalent.  Use the syntax that helps you see the purpose of the code.

 

Also Verilog 2001 came out a long time ago.  I'd suggest getting used to using the newer module port syntax:

 

module database

 (

    input wire [3:0] a,

    output reg [7:0] out1;

 );

 

This allows you to define the ports with their attributes on a single line, making it easier if you need to make changes, and making it easier to go back and quickly see what this module does.

 

Good luck.

-- Gabor

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Registered: ‎10-09-2013

Re: ERROR:HDLCompilers:26 - expecting '=', found '[

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thank you...

im trying intenciate this into another module.

such that it gives the next value of [x] every time

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Professor
Professor
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Registered: ‎08-14-2007

Re: ERROR:HDLCompilers:26 - expecting '=', found '[

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@warm.sky@hotmail.com wrote:

thank you...

im trying intenciate this into another module.

such that it gives the next value of [x] every time


That's a pretty vague description of what you want to do, perhaps if you give more detail we could help you?

-- Gabor
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