11-12-2010 11:21 PM
hi i write this cod dut it has an error please help me.
ERROR:HDLCompilers:26 - "alu.v" line 28 expecting 'endmodule', found 'case'
11-13-2010 12:32 AM - edited 11-13-2010 12:33 AM
You can't use a case-statement outside of a procedural block (remember that you'll have to declare "out" as reg then. Furthermore, use ANSI-style port lists. Result:
module alu ( input [3:0] a, b, input [2:0] m, output reg [3:0] out ); always @(*) begin case(m) 0: out=a; 1: out=a+b; 2: out=a-b; 3: out=a&b; 4: out=a|b; 5: out=a^b; 6: out=~a; default: out=b; endcase end endmodule
I also suggest that you get a good book on Verilog, or at least an online tutorial.
I will not send you an e-mail, though. Click on "Options" in the upper right corner, then on subscribe.
11-13-2010 04:15 PM
Adrian is correct. A good book should help you out with rules, however, you can get a lot of example within the ISE GUI. There's a section called language templates and this would have shown you that what you did is not allowed. The language templates is the button that has a yellow light bulb. Give this a try and you'll be surprised with how helpful this can be if you're not a coding expert.
Hope this helps.
03-27-2013 07:08 PM
could notfind module/primitive'registers r11'
could notfind module/primitive'registers r12'could notfind module/primitive'registers r13'
plz. reply to my error. i am using 10.1 Xilinx