01-11-2011 10:45 AM
I'm modifying a schematic designed by someone else in ISE 11.1 webpack. I had this error when synthesizing. The signal in the error is simply tied between VCC and the input of a submodule. That's it. There's no driver at all. The same circuit was succesfully compiled in another project. I'm confused.
01-11-2011 06:43 PM
Can you attach your project? Then we can reproduce the problem and try to help you.
01-13-2011 10:15 AM
Thanks for the offer. But I can't attach the project since it's proprietary.
I used Edit-Find to search the net name. There's only one wire found. The signal is used to enable a sub-circuit. It's a constant '1' and is not driven by anything.
01-13-2011 04:34 PM
You are synthesizing HDL code right?
When you say that you connected VCC to the enable pin, did you really mean that you assigned a logic 1 to the port like this.
VHDL enable => '1'
or did you do this some other way?
Have you examined the sub-module and confirmed that the enable pin is not assigned anywhere in the sub-module?
01-14-2011 02:42 PM
Synthesizing a schematic??? How, and maybe why, are you doing that?