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Observer
Observer
9,212 Views
Registered: ‎12-20-2007

ERROR:Xst:528 - Multi-source in Unit <TOPLEVEL> on signal <XLXN_3725>; this signal is connected to multiple drivers.

I'm modifying a schematic designed by someone else in ISE 11.1 webpack. I had this error when synthesizing. The signal in the error is simply tied between VCC and the input of a submodule. That's it. There's no driver at all. The same circuit was succesfully compiled in another project. I'm confused.

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Xilinx Employee
Xilinx Employee
9,202 Views
Registered: ‎05-14-2008

Can you attach your project? Then we can reproduce the problem and try to help you.

 

-Vivian

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Xilinx Employee
Xilinx Employee
9,189 Views
Registered: ‎08-23-2008

please check the answer record# 14264 < http://www.xilinx.com/support/answers/14264.htm >, this may help you.

 

Thanks

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Observer
Observer
9,150 Views
Registered: ‎12-20-2007

Thanks for the offer. But I can't attach the project since it's proprietary.

 

I used Edit-Find to search the net name. There's only one wire found. The signal is used to enable a sub-circuit. It's a constant '1' and is not driven by anything.

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Observer
Observer
9,149 Views
Registered: ‎12-20-2007

Thanks. I still don't find where my error came from. The signal is a wire between Vcc and the Enable input of a sub-circuit. It's not driven by anything.

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Xilinx Employee
Xilinx Employee
9,135 Views
Registered: ‎01-03-2008

You are synthesizing HDL code right?

 

When you say that you connected VCC to the enable pin, did you really mean that you assigned a logic 1 to the port like this.

 

Verilog   .enable(1'b1)

VHDL       enable => '1'

 

or did you do this some other way?

 

Have you examined the sub-module and confirmed that the enable pin is not assigned anywhere in the sub-module?

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Observer
Observer
9,118 Views
Registered: ‎12-20-2007

I'm synthesizing a schematic designed by someone else. VCC is connected to the Enable input of the submodule directly. It's not assigned anywhere else.

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Xilinx Employee
Xilinx Employee
9,110 Views
Registered: ‎01-03-2008

Synthesizing a schematic???  How, and maybe why, are you doing that?

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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