ERROR:Xst:528 - Multi-source in Unit <TOPLEVEL> on signal <XLXN_3725>; this signal is connected to multiple drivers.

[yangf3]

I'm modifying a schematic designed by someone else in ISE 11.1 webpack. I had this error when synthesizing. The signal in the error is simply tied between VCC and the input of a submodule. That's it. There's no driver at all. The same circuit was succesfully compiled in another project. I'm confused.

[viviany]

Can you attach your project? Then we can reproduce the problem and try to help you.

-Vivian

[sarithas]

please check the answer record# 14264 < http://www.xilinx.com/support/answers/14264.htm >, this may help you.

Thanks

[yangf3]

Thanks for the offer. But I can't attach the project since it's proprietary.

I used Edit-Find to search the net name. There's only one wire found. The signal is used to enable a sub-circuit. It's a constant '1' and is not driven by anything.

[yangf3]

Thanks. I still don't find where my error came from. The signal is a wire between Vcc and the Enable input of a sub-circuit. It's not driven by anything.

[mcgett]

You are synthesizing HDL code right?

When you say that you connected VCC to the enable pin, did you really mean that you assigned a logic 1 to the port like this.

Verilog   .enable(1'b1)

VHDL       enable => '1'

or did you do this some other way?

Have you examined the sub-module and confirmed that the enable pin is not assigned anywhere in the sub-module?

[yangf3]

I'm synthesizing a schematic designed by someone else. VCC is connected to the Enable input of the submodule directly. It's not assigned anywhere else.

[mcgett]

Synthesizing a schematic???  How, and maybe why, are you doing that?