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Visitor
Visitor
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Registered: ‎11-04-2013

ERROr:Assignment under multiple single edges is not supported for synthesis

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ERROR:HDLCompiler:1128 - "C:\Users\kokomama\Desktop\msa\memory\serial_2_parallel2_slave.v" Line 39: Assignment under multiple single edges is not supported for synthesis

 

i could not solve this error on the code below 

 

module serial_2_parallel2 #(parameter n= 16)

(
input [n-1:0] out_mem,
input [2:0] Nvn,
input clk,
input rst,
input validin,
output reg validout,
output reg [n-1:0] LLR_1,
output reg [n-1:0] LLR_2
);

reg flag;
reg [n-1:0] reg_mem_1;
reg [n-1:0] reg_mem_2;
reg [n-1:0] reg_mem_3;
reg [n-1:0] reg_mem_4;
reg [n-1:0] reg_mem_5;
reg [n-1:0] reg_mem_6;
reg [n-1:0] reg_mem_7;
reg [2:0] j;
reg [2:0] i;
reg [2:0] k;

always@(posedge clk or negedge rst)
begin
if(!rst)
begin
i=0;
j=0;
flag=0;
validout= 0;
end
if (Nvn % 2 == 1 && i== 0) //if odd, add 1
begin
k = Nvn+1;
end
else if (Nvn % 2 == 0 && i== 0) //if even
begin
k = Nvn;
end

if (validin == 1) //reading cycle
begin
case (i)
3'b000 : begin
reg_mem_1 = out_mem;
flag = 1 ;
i = i+1;
end

3'b001 : begin
reg_mem_2 = out_mem;
i = i+1;
end
3'b010 : begin
reg_mem_3 = out_mem;
i = i+1;
end
3'b011 : begin
reg_mem_4 = out_mem;
i = i+1;
end
3'b100 : begin
reg_mem_5 = out_mem;
i = i+1;
end

3'b101 : begin
reg_mem_6 = out_mem;
i = i+1;
end
3'b110 : begin
reg_mem_7 = out_mem;
i = i+1;
end
default
begin
reg_mem_1=0;
reg_mem_2=0;
reg_mem_3=0;
reg_mem_4=0;
reg_mem_5=0;
reg_mem_6=0;
reg_mem_7=0;

end
endcase
end

if (flag && (i > k /2 -1 )) //writing
begin
case (j)
3'b000 : begin
LLR_1 = reg_mem_1;
LLR_2 = reg_mem_2;
flag = 1;
validout = 1;
j = j+1;
end

3'b001 : begin
LLR_1 = reg_mem_3;
LLR_2 = reg_mem_4;
j = j+1;
end

3'b010 : begin
LLR_1 = reg_mem_5;
LLR_2 = reg_mem_6;
j = j+1;
end

3'b011 : begin
LLR_1 = reg_mem_7;
end
default
begin
LLR_1 = 0;
LLR_2 = 0;
end
endcase
end

 

if ( j == k/2 ) //reset
begin
i=0;
j=0;
flag=0;
validout= 0;
end
end

endmodule

 

please any help

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Teacher
Teacher
3,542 Views
Registered: ‎03-31-2012

Re: ERROr:Assignment under multiple single edges is not supported for synthesis

Jump to solution
After your "if (!rst)" put an "else" and everything put all the lines in that else statement. ie:
if (!rst) begin
...
end else begin
... // everything goes here
end
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

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Highlighted
Teacher
Teacher
3,543 Views
Registered: ‎03-31-2012

Re: ERROr:Assignment under multiple single edges is not supported for synthesis

Jump to solution
After your "if (!rst)" put an "else" and everything put all the lines in that else statement. ie:
if (!rst) begin
...
end else begin
... // everything goes here
end
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post

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