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Adventurer
Adventurer
2,841 Views
Registered: ‎11-04-2010

EXCEPTION_ACCESS_VIOLATION during JTAG AXI Master core synthesis in 2015.3

Hi,

I've seen several forum threads about EXCEPTION_ACCESS_VIOLATION, but they seem to be isolated cases. In our case, we have a nightly build of the current state of our FPGA, which has been running OK for a while. But recently we've started to have these failures over and over again, while building the same IP core. I'm hoping someone at Xilinx can take a look at the .dmp file and provide insight. (By the way, I have run a memory diagnostic on the build machine, which passed.)

The attached ZIP file contains:

Archive:  20161212a.zip
Zip file size: 59867 bytes, number of entries: 4
-rw-r--r--  3.0 unx   155940 bx defN 16-Dec-09 22:19 hs_err_pid2752.dmp
-rw-r--r--  3.0 unx      143 tx defN 16-Dec-09 22:19 hs_err_pid2752.log
-rw-r--r--  3.0 unx   605553 tx defN 16-Dec-12 10:00 build.txt
-rw-r--r--  3.0 unx     5871 tx defN 16-Dec-09 22:16 jtag_axi_0.xci
4 files, 767507 bytes uncompressed, 59215 bytes compressed:  92.3%
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Moderator
Moderator
2,798 Views
Registered: ‎07-21-2014

Re: EXCEPTION_ACCESS_VIOLATION during JTAG AXI Master core synthesis in 2015.3

@vertreko

 

I am able to synthesize the shared .xci file at my end without any issues. Looks like machine specific issue to me, can you let us know which OS you are targeting?

 

Thanks,
Anusheel
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Adventurer
Adventurer
2,771 Views
Registered: ‎11-04-2010

Re: EXCEPTION_ACCESS_VIOLATION during JTAG AXI Master core synthesis in 2015.3

Anusheel,

I'm running Windows 7 Professional Service Pack 1. I was hoping one of the Vivado developers could take a look at the .dmp file and look for clues about where/why it crashed.

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