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Adventurer
Adventurer
3,000 Views
Registered: ‎11-22-2016

Edge Detection - Question

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Hello All,

This question has been poking me for a while, So I need help.

 

Say if I have a 100 Mhz input clock to my FPGA, and say I am getting another input signal named slave_interrupt, from a slave device. 

 

If I want to detect the positive edge of the slave_interrupt from the slave device, why do I need to design an edge detector circuit?. What if I just go with the following?

always @posedge(slave_interrupt) in verilog

if rising_edge(slave_interrupt) in VHDL?

 

Why can't I use the above method of coding?.

 

Thanks,

Manoj

 

 

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Scholar u4223374
Scholar
5,394 Views
Registered: ‎04-26-2015

Re: Edge Detection - Question

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That works OK, with two limitations:

 

(1) It's not in the same clock domain as the rest of your design. Any signals going from that block to another block (on the 100MHz clock) have unknown (undefined) timing and therefore can't be proven to meet timing requirements. In practice, this means that it'll probably work ... most of the time.

 

(2) Last time I checked, the Xilinx tools complained about clocking flipflops from pins that aren't actually designed for clock input.

 

Bringing them into the 100MHz clock domain immediately using an edge detector solves both problems.

4 Replies
Scholar u4223374
Scholar
5,395 Views
Registered: ‎04-26-2015

Re: Edge Detection - Question

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That works OK, with two limitations:

 

(1) It's not in the same clock domain as the rest of your design. Any signals going from that block to another block (on the 100MHz clock) have unknown (undefined) timing and therefore can't be proven to meet timing requirements. In practice, this means that it'll probably work ... most of the time.

 

(2) Last time I checked, the Xilinx tools complained about clocking flipflops from pins that aren't actually designed for clock input.

 

Bringing them into the 100MHz clock domain immediately using an edge detector solves both problems.

Explorer
Explorer
2,964 Views
Registered: ‎04-12-2017

Re: Edge Detection - Question

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The 'rising_edge' function is used to describe a CLOCK signal on a design.

 

If you used the interrupt as a clock signal... what would be your data signal?

 

Apart from that, I agree with the other arguments you were already given.

Avi Chami MSc
FPGA Site
Scholar markcurry
Scholar
2,951 Views
Registered: ‎09-16-2009

Re: Edge Detection - Question

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Don't do that.

 

Avoid doing that at all possible cost, unless you have no alternative.  (And there likely are alternatives).  And then if you do, you're going to need to seriously sharpen your pencil to make sure it'll work reliably.

 

Why shouldn't you do that?  It's not following basic synchronous design principles.  Simple as that.

 

Is the signal in question generated synchronously with the 100 MHz clock?  At what rate?  Is there a timing specification for the signal in question with respect to the clock?

 

Start with those questions.  The decision tree for your solution forks quite a bit depending on the answers to those questions.

 

Regards,

 

Mark

 

Adventurer
Adventurer
2,934 Views
Registered: ‎11-22-2016

Re: Edge Detection - Question

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Thank you everyone.

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