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slal
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Registered: ‎04-04-2010

Effect of XST trimming

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Trying to implement a DSP algorithm on Virtex-5. Would like to inhibit Xilinx ISE from doing the following optimization tasks:

 

 

Xst: 646 - Signal <signal_bus> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

 

 

In the event that such optimization trimming can not be avoided, does the synthesized/implemented logic act differently?

 

For example, consider a simple count-up-by-4 counter. The least significant two bits are always zero, and XST thus trims them out during optimization. Does this have an effect on the overall logic, and if so then how can such a counter be realized? Is it valid to increment by 1 every time, and then just shift left by 2 bits?

 

Thanks!

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luisb
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Registered: ‎04-06-2010

Using a KEEP constraint in your RTL should prevent this.

You can read about this constraint in the constraints guide on page 114: http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf

 

 For VHDL:

attribute keep : string;

attribute keep of signal_bus : signal is "true";

 -- make sure have this just below the signal declaration

 

For Verilog:

//place this constraint immediately before the declaration of the signal

(* KEEP = "TRUE"*) 

 

 

Even though XST trims out the logic, it doesn't mean that the logic has changed. It will correctly count to the value that you specified in your code.  XST can do this by inferring some of the FPGA primitives that essentially give the same outputs without using all of the signals.  

 

Hope this helps. 

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luisb
Xilinx Employee
Xilinx Employee
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Registered: ‎04-06-2010

Using a KEEP constraint in your RTL should prevent this.

You can read about this constraint in the constraints guide on page 114: http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf

 

 For VHDL:

attribute keep : string;

attribute keep of signal_bus : signal is "true";

 -- make sure have this just below the signal declaration

 

For Verilog:

//place this constraint immediately before the declaration of the signal

(* KEEP = "TRUE"*) 

 

 

Even though XST trims out the logic, it doesn't mean that the logic has changed. It will correctly count to the value that you specified in your code.  XST can do this by inferring some of the FPGA primitives that essentially give the same outputs without using all of the signals.  

 

Hope this helps. 

View solution in original post

bassman59
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Registered: ‎02-25-2008

slal wrote:

Trying to implement a DSP algorithm on Virtex-5. Would like to inhibit Xilinx ISE from doing the following optimization tasks:

 

 

Xst: 646 - Signal <signal_bus> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

 

 

In the event that such optimization trimming can not be avoided, does the synthesized/implemented logic act differently?

 

For example, consider a simple count-up-by-4 counter. The least significant two bits are always zero, and XST thus trims them out during optimization. Does this have an effect on the overall logic, and if so then how can such a counter be realized? Is it valid to increment by 1 every time, and then just shift left by 2 bits?

 

Thanks!


The optimization helps in two ways: one, it saves resources because two never-changing flip-flops don't have to be used, and two, the counter can be faster because  there's less logic involved.

 

In general, if the tools detect that a signal has no load, then it is optimized away and it has no affect on the design because the signal is never used!

 

In the case of your count-by-four, it does get turned into a simple increment-by-one counter, but again, since for whatever reason your logic never uses the two LSbs, your design is unaffected.

 

Now if your design, for whatever reason, DOES use the two LSbs of this count-by-four counter, the tools will throw away flip-flops that would otherwise be used for the LSbs and replace them with hardwired X_VCC (logic 1) or X_GND (logic 0) inputs to whatever logic uses that counter. You'll see a message indicating that the flip-flop was replaced by the constant. The value of the two lowest bits is then wholly determined by their initialization value.

----------------------------Yes, I do this for a living.
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slal
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Registered: ‎04-04-2010

Your comments are really helpful. The count-up-by-4 counter is actually being used to address a RAM block which is storing 4 values at a time. What I am trying to do is something similar to the following:

 

 

data_RAM[ index ] <= datain1;

data_RAM[ index+1 ] <= datain2;

data_RAM[ index+2 ] <= datain3;

data_RAM[ index+3 ] <= datain4;

index <= index + 4; // this is why the bottom two LSBs are being trimmed, although I technically am using them!

 

Any suggestions?

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bassman59
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Registered: ‎02-25-2008

slal wrote:

Your comments are really helpful. The count-up-by-4 counter is actually being used to address a RAM block which is storing 4 values at a time. What I am trying to do is something similar to the following:

 

 

data_RAM[ index ] <= datain1;

data_RAM[ index+1 ] <= datain2;

data_RAM[ index+2 ] <= datain3;

data_RAM[ index+3 ] <= datain4;

index <= index + 4; // this is why the bottom two LSBs are being trimmed, although I technically am using them!

 

Any suggestions?


Is data_RAM an actual RAM, or is it just a bunch of flip-flops?

You cannot assign simultaneously to more than one location in a RAM.

Look at what the synthesis tool created!

----------------------------Yes, I do this for a living.
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slal
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Registered: ‎04-04-2010
My bad I called it data_RAM. It isn't really any actual RAM. It does infact infer flip-flops, because it's just a small amount of memory I need. However, my main concern is whether the flops will be addressed properly or not.
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bassman59
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Registered: ‎02-25-2008

slal wrote:
My bad I called it data_RAM. It isn't really any actual RAM. It does infact infer flip-flops, because it's just a small amount of memory I need. However, my main concern is whether the flops will be addressed properly or not.

Simulate it and see.

----------------------------Yes, I do this for a living.
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slal
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Registered: ‎04-04-2010

I have simulated everything using the ISE Simulator. The results are fine. But post XST synthesis, the registers being trimmed were my concern. However, thanks to your discussions I have managed to improve other parts of the design. luisb's suggestion about using "KEEP" works well too, and XST stopped giving any warnings on trimming.

Thank you everyone!

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