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Visitor hossein1387
Visitor
310 Views
Registered: ‎07-06-2018

Elaborated Designed is omitted in Synthesis

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I am trying to sythesize my design in Vivado 2019 webpack edition. My design has 6 submodules: alu, d_mem, decoder, i_mem, regfile, next_pc_cal. The Figure below shows the design after elaboration:

elab.png

 

And the following is after synthesis:

 

synth.png

 

If you look closely to the netlist in both elaboratio and synthesis, you can see that only d_mem, i_mem regfile and decoder are syntheised. On the other hand the device usage is suspicosly low which indicates the synthesizer have omitted most of the logic. I have 212 warning messages which 200 of them are coming from the xilinx bram IP I used in my design. And I found the other warnings are not important. I really dont know what I am missing at this point.

 

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Visitor mfiorentino
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Registered: ‎10-24-2014

Re: Elaborated Designed is omitted in Synthesis

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Hello Hossein,

From the information you gave us, it is difficult to say if your synthesized design has a problem or not. It would help to have synthesis reports (log, area report, timing report, etc.) instead of the screenshot which, in my opinion, do not provide any usefull inofrmation.

The fact that some of your modules have disapeared from the list post-synthesis is not necessarily a problem. By default, the synthesis tool optimizes your design in a way that lead to the best performances. For example, if merging the alu with the top level can reduce the number of signals and decrease the latency of some paths then it will do it. It is called ungrouping. Unless you have specified some constraints in your xdc that prevents this behavior, it seems ok to me.

Then you mention a suspiciously low device usage, but I cannot see the value on the screenshot... (cf my first remark).

I think that the easiest way for you to make sure that the synthesis went ok is to run a post-synthesis simulation. Since you seem to have pretty elaborated test of the behavioral model, you should take advantage of them to verify your design post-synthesis.

If it does not work it does not necessarily mean that the synthesis went wrong. For example, it can be due to timing: make sure that the static timing analysis (STA) gives you a positive slack for all your clocks, and make sure that your test bench uses a clock with a large enough period.

Hope this helps,

Mickael

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Teacher drjohnsmith
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Registered: ‎07-09-2009

Re: Elaborated Designed is omitted in Synthesis

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Sorry, when I zoom in to try to read this , its just fuzzy

Normal way of designing is to simulate before you synthesise,

If you simulate you will find out if your design works,
My bet is you have a feature or two thats meaning the design is not as you think , and simulation allows you to zoom in to signals to see whats happening

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor hossein1387
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Registered: ‎07-06-2018

Re: Elaborated Designed is omitted in Synthesis

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Thanks for your reply, its actualy a riscv processor and I have extensively verified my design. The design passes riscv tests. I also have a behavioral prediciton model implemented in my verification suite to catch any behavioral bugs. The reason I added the images was to show the messages that I am seeing. I believe going through schematic is not practical in a post like this. Is there any way that I can force the synthesis tool not to optmize? Also, why I am not getting any message regrading omitting these submodules? I have no critical warning and no errors. The messages in warning and info are also useless.

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Visitor mfiorentino
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Registered: ‎10-24-2014

Re: Elaborated Designed is omitted in Synthesis

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Hello Hossein,

From the information you gave us, it is difficult to say if your synthesized design has a problem or not. It would help to have synthesis reports (log, area report, timing report, etc.) instead of the screenshot which, in my opinion, do not provide any usefull inofrmation.

The fact that some of your modules have disapeared from the list post-synthesis is not necessarily a problem. By default, the synthesis tool optimizes your design in a way that lead to the best performances. For example, if merging the alu with the top level can reduce the number of signals and decrease the latency of some paths then it will do it. It is called ungrouping. Unless you have specified some constraints in your xdc that prevents this behavior, it seems ok to me.

Then you mention a suspiciously low device usage, but I cannot see the value on the screenshot... (cf my first remark).

I think that the easiest way for you to make sure that the synthesis went ok is to run a post-synthesis simulation. Since you seem to have pretty elaborated test of the behavioral model, you should take advantage of them to verify your design post-synthesis.

If it does not work it does not necessarily mean that the synthesis went wrong. For example, it can be due to timing: make sure that the static timing analysis (STA) gives you a positive slack for all your clocks, and make sure that your test bench uses a clock with a large enough period.

Hope this helps,

Mickael

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

Re: Elaborated Designed is omitted in Synthesis

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@hossein1387 wrote:

Thanks for your reply, its actualy a riscv processor and I have extensively verified my design. The design passes riscv tests. 


 How do you run the riscv tests? Is it a Hardware test with the bit file download to the FPGA?

You can change synthesis option -flatten_hierarchy to none and run Synthesis to see if the 6 modules are all kept.

And compare the resource utilization after Synthesis with the run with -flatten_hierarchy set to rebuilt.

If the resource utilization of the two runs is more or less the same, Synthesis is probably doing nothing wrong but just not rebuilding the hierarchies of the two lost modules due to cross hierarchy boundary optimization.

-vivian

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Visitor hossein1387
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Registered: ‎07-06-2018

Re: Elaborated Designed is omitted in Synthesis

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Thanks to @viviany and @mfiorentino it turns out I was flattening my design after synthesis which is the default option. I found out to debug timing constraint, its easier to follow traces when the design is not flattened, once I was satisfied with timing, I turned it back to its default configuration. Because of cross hierarchy boundary optimization, you would see a better performance after doing so (at least this was the case for me).
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