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4,464 Views
Registered: ‎08-11-2017

Elaboration system task in SystemVerilog

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I'm trying to synthesize the following SystemVerilog module in Vivado:

 

module ok_trigger_in #(addr=8'h40) (
    ok_ep_bus.ep ep,
    input bit clk,
    output bit [31:0] dout
    );

    if (addr < 8'h40 || addr > 8'h5f)
        $fatal(0, "Bad address for okTriggerIn. Correct address range is 0x40 - 0x5F.");

    okTriggerIn u_ep(.okHE(ep.HE), .ep_addr(addr), .ep_clk(clk), .ep_trigger(dout));
endmodule

 

Vivado synthesis prints: "WARNING: [Synth 8-1921] elaboration system task fatal violates IEEE 1800 syntax" and ignores the line. (i.e. when I instantiate the module with a bad value of the "addr" parameter, it does not stop synthesis.)

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Xilinx Employee
Xilinx Employee
4,316 Views
Registered: ‎01-11-2011

Currently Vivado does not support the $fatal SystemVerilog system task. However in 2017.x versions, we do have limited capabilities for messaging similar to $fatal, by using $info, $warning, and $error.

 

$info("info");
$warning("warning");
$error("error");

 

INFO: [Synth 8-5572] Synth: info
WARNING: [Synth 8-5572] Synth: warning
ERROR: [Synth 8-5572] Synth: error

 

$error will stop Synthesis from completing. Note that this is supported only within initial blocks, and can only be used to evaluate constant expressions; for example, parameters. This is also noted in the Synthesis User Guide for 2017.4 (http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug901-vivado-synthesis.pdf).

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9 Replies
Scholar
Scholar
4,435 Views
Registered: ‎09-16-2009

 

Which version of Vivado?  I believe they added this support in 2017.1.  It was a missing feature that was available in ISE that is/was missing in Vivado.  I can dig through some notes to confirm, but check your Vivado version and/or try the latest version.

 

Regards,

 

Mark

 

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4,419 Views
Registered: ‎08-11-2017

I am on 2017.1. I couldn't find any mention of it in the 2017.2 release notes.

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Visitor
Visitor
4,044 Views
Registered: ‎10-23-2017

This issue is also present in 2017.4

The syntax looks right according to IEEE std 1800-2005 which the warning is referring to

fatal_message_task ::= $fatal [ ( finish_number [ , message_argument { , message_argument } ] ) ] ;

— $fatal shall generate a run-time fatal assertion error, which terminates the simulation 
with an error code. The first argument passed to $fatal shall be consistent with the corresponding
argument to the Verilog $finish system task, which sets the level of diagnostic information reported
by the tool. Calling $fatal results in an implicit call to $finish.
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Highlighted
Xilinx Employee
Xilinx Employee
4,317 Views
Registered: ‎01-11-2011

Currently Vivado does not support the $fatal SystemVerilog system task. However in 2017.x versions, we do have limited capabilities for messaging similar to $fatal, by using $info, $warning, and $error.

 

$info("info");
$warning("warning");
$error("error");

 

INFO: [Synth 8-5572] Synth: info
WARNING: [Synth 8-5572] Synth: warning
ERROR: [Synth 8-5572] Synth: error

 

$error will stop Synthesis from completing. Note that this is supported only within initial blocks, and can only be used to evaluate constant expressions; for example, parameters. This is also noted in the Synthesis User Guide for 2017.4 (http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug901-vivado-synthesis.pdf).

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Adventurer
Adventurer
515 Views
Registered: ‎09-10-2019

[Synth 8-1921] elaboration system task fatal violates IEEE 1800 syntax

$fatal( 1, "Invalid BUFFER_SIZE - must be power of 2 - aborting" );

Vivado 2019.2

3 years later, where are we with that system task?

> Currently Vivado does not support the $fatal SystemVerilog system task.

=> Why does Vivado warn the code "violates the IEEE 1800 syntax" if it's a Vivado's lack of IEEE1800 support?

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Scholar
Scholar
478 Views
Registered: ‎09-16-2009

FYI, Xilinx does have a CR for fixing these errant messages emitted from Vivado:

[Synth 8-1921] elaboration system task fatal violates IEEE 1800 syntax

Vivado is emitting these warnings incorrectly (i.e. the syntax is correct, But Vivado says it's incorrect).  Curiously, even after emitting this warning message, vivado displays, the $info, $warning, and $error correctly.

I filed the ticket back in March 2020, and a CR was generated.

I'm not certain about the support for $fatal.

Regards,

Mark

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Adventurer
Adventurer
457 Views
Registered: ‎09-10-2019

Well, this ticket shows Xilinx has been aware since 2017 and it was supposed to be fixed in 2017.x.

Now we know but wasted time.

Regards,

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Scholar
Scholar
446 Views
Registered: ‎09-16-2009

Well, to be a little more fair, it was two separate items:

  1. Supporting those elaboration task - Which Vivado does in 2017.x for $error, $warning, and $info.  (I'm not sure why $fatal was left off the list)
  2. Not emitting an incorrect warning (but otherwise working fine for the above)

The CR that was generated for me in March was just regarding item (2).  And to be clear, Vivado is emitting the incorrect warning in the use case of any of those elaboration system task ($error, $info, $warning).

I need to check on the support for $fatal - I think I might be using it too, but haven't looked close enough.  In truth these "elaboration time" assertions are going to be cleaned up in simulation, so that by the time one get's to synthesis, it should never fire. Hence my uncertainty on Vivado support...

Regards,

Mark

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Adventurer
Adventurer
412 Views
Registered: ‎09-10-2019
Markcurry,
I guess you're a Xilinx employee. As for me, I'm not interested in finding Vivado's bugs or trying to figure out whether Vivado is lying.
I'm just seeing 3years later, this wrong warning still shows up. The reason behind that is Xilinx's business, not user's business.

You tell me no big deal, that doesn't lead to errors and it works properly.
1. How are we suppose to know? Should I unit test Vivado by myself?
2. I had to find this post telling this issue was supposed to be solved 3years ago, why implementing the feature without removing the misleading warning?
3. In an ideal world with lots of people in your team and time you can run a simulation of everything. In reality, you don't.

Anyway, thank you for you answers
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