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Registered: ‎08-11-2017

Elaboration system task in SystemVerilog

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I'm trying to synthesize the following SystemVerilog module in Vivado:

 

module ok_trigger_in #(addr=8'h40) (
    ok_ep_bus.ep ep,
    input bit clk,
    output bit [31:0] dout
    );

    if (addr < 8'h40 || addr > 8'h5f)
        $fatal(0, "Bad address for okTriggerIn. Correct address range is 0x40 - 0x5F.");

    okTriggerIn u_ep(.okHE(ep.HE), .ep_addr(addr), .ep_clk(clk), .ep_trigger(dout));
endmodule

 

Vivado synthesis prints: "WARNING: [Synth 8-1921] elaboration system task fatal violates IEEE 1800 syntax" and ignores the line. (i.e. when I instantiate the module with a bad value of the "addr" parameter, it does not stop synthesis.)

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Xilinx Employee
Xilinx Employee
3,796 Views
Registered: ‎01-11-2011

Re: Elaboration system task in SystemVerilog

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Currently Vivado does not support the $fatal SystemVerilog system task. However in 2017.x versions, we do have limited capabilities for messaging similar to $fatal, by using $info, $warning, and $error.

 

$info("info");
$warning("warning");
$error("error");

 

INFO: [Synth 8-5572] Synth: info
WARNING: [Synth 8-5572] Synth: warning
ERROR: [Synth 8-5572] Synth: error

 

$error will stop Synthesis from completing. Note that this is supported only within initial blocks, and can only be used to evaluate constant expressions; for example, parameters. This is also noted in the Synthesis User Guide for 2017.4 (http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug901-vivado-synthesis.pdf).

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Scholar
Scholar
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Registered: ‎09-16-2009

Re: Elaboration system task in SystemVerilog

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Which version of Vivado?  I believe they added this support in 2017.1.  It was a missing feature that was available in ISE that is/was missing in Vivado.  I can dig through some notes to confirm, but check your Vivado version and/or try the latest version.

 

Regards,

 

Mark

 

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Highlighted
3,899 Views
Registered: ‎08-11-2017

Re: Elaboration system task in SystemVerilog

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I am on 2017.1. I couldn't find any mention of it in the 2017.2 release notes.

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Visitor
Visitor
3,524 Views
Registered: ‎10-23-2017

Re: Elaboration system task in SystemVerilog

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This issue is also present in 2017.4

The syntax looks right according to IEEE std 1800-2005 which the warning is referring to

fatal_message_task ::= $fatal [ ( finish_number [ , message_argument { , message_argument } ] ) ] ;

— $fatal shall generate a run-time fatal assertion error, which terminates the simulation 
with an error code. The first argument passed to $fatal shall be consistent with the corresponding
argument to the Verilog $finish system task, which sets the level of diagnostic information reported
by the tool. Calling $fatal results in an implicit call to $finish.
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Xilinx Employee
Xilinx Employee
3,797 Views
Registered: ‎01-11-2011

Re: Elaboration system task in SystemVerilog

Jump to solution

Currently Vivado does not support the $fatal SystemVerilog system task. However in 2017.x versions, we do have limited capabilities for messaging similar to $fatal, by using $info, $warning, and $error.

 

$info("info");
$warning("warning");
$error("error");

 

INFO: [Synth 8-5572] Synth: info
WARNING: [Synth 8-5572] Synth: warning
ERROR: [Synth 8-5572] Synth: error

 

$error will stop Synthesis from completing. Note that this is supported only within initial blocks, and can only be used to evaluate constant expressions; for example, parameters. This is also noted in the Synthesis User Guide for 2017.4 (http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug901-vivado-synthesis.pdf).

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