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Anonymous
Not applicable
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Endless synthesis loop ISE - verilog parameter passing

I am using ISE 11.2. I am instantiating a FIFO 9 times in my design. I am passing data width, address width and fifo depth through parameters as each FIFO has different sizes. Instantiation is as follows:

 

sync_fifo # (35,3,8) sync_cmd_fifo // to store commands for memory after port width adjustment
(
    .reset(mc_bond_reset),                
    .clk(mc_bond_clk),
    .fifo_wr_data(vdc1_scmdf_data_in),
    .fifo_wr(vdc1_scmdf_wr),
    .fifo_rd_data(vdc1_scmdf_data_out),
    .fifo_rd(vdc1_scmdf_rd),
    .fifo_empty(vdc1_scmdf_empty),
    .fifo_full(vdc1_scmdf_full)     
);

With this type of coding, synthesis goes in infinite loop, no warnings or messages shown. It is stuck at translation phase.

But when I instantiate without passing any parameters, as follows:

sync_fifo sync_cmd_fifo // to store commands for memory after port width adjustment

(
    .reset(mc_bond_reset),                
    .clk(mc_bond_clk),
    .fifo_wr_data(vdc1_scmdf_data_in),
    .fifo_wr(vdc1_scmdf_wr),
    .fifo_rd_data(vdc1_scmdf_data_out),
    .fifo_rd(vdc1_scmdf_rd),
    .fifo_empty(vdc1_scmdf_empty),
    .fifo_full(vdc1_scmdf_full)     
);

Here I am not passing any parameters, synthesis completes successfully in 2-3 mins. How can I resolve this problem?

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3 Replies
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Professor
Professor
5,865 Views
Registered: ‎08-14-2007

. . .

sync_fifo # (35,3,8) sync_cmd_fifo // to store commands for memory after port width adjustment
(


Positional arguments are not considered good practice in general.  Are you sure that the

parameters you are passing are going to the correct underlying parameter in module

sync_fifo?  For example if you think you're making a fifo with data width 35, but the actual

first parameter arguiment is the depth you could run into problems with unsupported

parameter values.

 

Regards,

Gabor

-- Gabor
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Anonymous
Not applicable
5,836 Views

Thanks for your comments. I realised that when I set the fifo_depth to 1024, synthsis goes on for hours, havent seen it end. But if I change it to 8 , synthesis is completed in 2-3 mins. btw, I am using the async fifo design from sunburst.
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Visitor
Visitor
5,785 Views
Registered: ‎12-18-2009

While mapping the parameter you have to to care. You have to avoid positional mapping.

This is common problem in passing parameters

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