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308 Views
Registered: ‎05-23-2019

Error_design clock consistency

Hello,

I created a simple adder ip based on option "Create and Package new IP" in vivado, so I am trying to make simple design ( depicted below), in order to laverage partial reconfiguration, but it doesn't have consistency between clocks of IP signals, in below errors are denoted well in image, so do yu have any idea how to solve this issue ? thanks in advance error_design.jpg

 

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Moderator
Moderator
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Registered: ‎01-16-2013

@tarek.elouaret 

 

Your custom IP has multiple drivers for a net. Check and fix them before packaging the IP. 

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Registered: ‎05-23-2019

Hi @syedz Thanks for your reply, the fact, how may I fix them, could yu show me how ? thanks 

 

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