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Visitor minshad11
Visitor
237 Views
Registered: ‎04-10-2019

Error during Synthesis-XST. What it refers to ?

1 : Port OUT must not be declared to be an array
2 : Cannot assign to memory OUT directly
3 : Cannot assign a packed type to an unpacked type
4 : Cannot access memory OUT directly
5 : Cannot assign an unpacked type to a packed type
6 : Procedural assignment to a non-register OUT is not permitted, left-hand side should be                 reg/integer/time/genvar
7 : Procedural assignment to a non-register OUT is not permitted, left-hand side should be     reg/integer/time/genvar
8 : Instantiation is not allowed in sequential area except checker instantiation
9 : Module <STATE> ignored due to previous errors.

# when i give "reg" type they are saying it should be net type, and when i give net type (wire) they are saying error as in error 6 above. I cant fix these errors above. When I try to fix, they are showing different error at the same line.

#immediate help needed...

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6 Replies
Scholar dpaul24
Scholar
229 Views
Registered: ‎08-07-2014

Re: Error during Synthesis-XST. What it refers to ?

@minshad11,

I cant fix these errors above.

You have not provided the RTL. I would suggest you to update you Verilog skills and use a good coding style to avoid such errors during synthesis.

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Moderator
Moderator
197 Views
Registered: ‎05-02-2017

Re: Error during Synthesis-XST. What it refers to ?

 

hi @minshad11 ,

 

Please see the below link to know for basic coding tech used in xilinx FPGA 

 

https://www.xilinx.com/video/hardware/basic-hdl-coding-techniques.html

 

Regards
Chandra sekhar
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Xilinx Employee
Xilinx Employee
144 Views
Registered: ‎05-14-2008

Re: Error during Synthesis-XST. What it refers to ?

Most of these are basic HDL syntax issue.

The data type (reg or wire) also needs to work with different assignment operators like "=" and "<=". So I guess sometimes you need to not only to change the data type but also need to change the way you use it.

You can find an HDL book to learn or do some search online. For example, you can search for "unpacked type" and "packed type" to learn what they are referring to.

You can also learn from some existing coding examples. UG687 has some coding examples that fit for Xilinx FPGA designs.

-vivian

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Visitor minshad11
Visitor
121 Views
Registered: ‎04-10-2019

Re: Error during Synthesis-XST. What it refers to ?

 
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Xilinx Employee
Xilinx Employee
112 Views
Registered: ‎05-14-2008

Re: Error during Synthesis-XST. What it refers to ?

77: assign j = 8'b0;
79: assign ADD = 32'b00000000000000000000000011111111;

In the first two errors, "concurrent assignment" is referring to “assign” statement in the above two lines. Only wire (net) type can be used in this way. Or on the other hand, reg type cannot be used with "assign" statement. Are you giving initial value to j and ADD? If so, you can do it in the way below:

72: reg [7:0] j = 8'b0;
74: reg [31:0] ADD = 32'b00000000000000000000000011111111;

This is the right way to give initial value to a reg type.

 

71: inout wire [31:0] PRNG_OUT [127:0];

80: always @(SEED)
81: begin
82: while(j<=127)
83: begin
84: FEEDBACK = ADD & PRNG_OUT [j]; // adding last 8 bits of previous output to generate new output
85: PRNG_OUT[j+1'b1] = (FEEDBACK + (((SEED+2)*(SEED*2))*(SEED**SEED))); // producing random number
86: j = j + 1'b1;
87: end
88: end

PRNG_OUT is a wire type. A wire type cannot be used in always block. You should declare it as reg type:

71: inout reg [31:0] PRNG_OUT [127:0];

What's more, the way you're coding is more like C style (while loop). The more common Verilog way is to use generate statement and for loop.

 

92: always @(m)
93: begin
94: BUFFER send2(.k(m));
95: end

"94: BUFFER send2(.k(m));"  is enough for submodule instantiation. You don't need the always block here.

 

I suggest you learn from the coding examples in UG687 first. You'll find those rulls in those examples.

-vivian

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Visitor minshad11
Visitor
61 Views
Registered: ‎04-10-2019

is while loop synthesizable in verilog ?

 
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