02-14-2018 09:12 AM
I'm doing the design with some vendor IP. I am using Vivado 2017.2 and Windows 10. When I set verilog as target language, everything works well. But if I changed to VHDL, I will get the following errors when generating output products. The error seems sporadic, because sometimes it worked fine. Also it always worked on Linux. I suspect it could be my environment issue. Can someone help?
Here are the errors:
[IP_Flow 19-3286] Unsupported VHDL data type 'INTEGER' for bool value.
[IP_Flow 19-153] Failed to convert bool value 'false' to HDL value.
[IP_Flow 19-153] Failed to convert bool value 'true' to HDL value.
(16 similar errors within above)
02-14-2018 09:17 AM
Can you show us how INTEGER is set or defined in RTL? Found the following related Answer record:
02-14-2018 09:53 AM
Thank you for your quick reply.
That answer record help me less...
The problematic IP is in Verilog, and the IP packager defines bool type for some parameters. see the attachment. When Vivado generates the wrapper VHDL for the IP, it seems unable to translate these parameter to 'INTEGERS' as generic,because I don't find these parameter defined in the auto generated VHDL.
This is what I found. Thanks!
02-14-2018 08:04 PM
Glad to know the shared answer record helped. Please close this forum thread by marking the post as "Accept as solution"
02-16-2018 11:33 AM
02-20-2018 08:15 AM