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4,677 Views
Registered: ‎11-05-2013

Error in Viewing RTL Schematic

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Thisi is my code created on Xilinx ISE Design Suite 14.5. But when I try to view the RTL Schematic, I get the following error: 

Line 9: Signal Ty in unit Timers_Test is connected to following multiple drivers:

 

I am not able to find the solution to this error.. Please help me.

 

 

`timescale 1ns / 1ps


module Timers_Test(st, clk, Ty, Tg);
input st, clk;
output reg Ty;
output reg Tg;
reg [4:0] value=5'b00000;


always@(posedge clk) begin


case(value)
5'b00011:Ty<=1;
5'b10100:Tg<=1;
default: begin
Ty<=0;
Tg<=0;
end
endcase

value<=value+1;
end

always@(posedge st) begin
value<=0;
Ty<=0;
Tg<=0;
end

 

endmodule

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Teacher
Teacher
5,812 Views
Registered: ‎03-31-2012

Re: Error in Viewing RTL Schematic

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I think the error is pretty clear. You are assigning to Ty in multiple processes so there are multiple drivers. You have the "posedge clk" process and "posedge st" process which are both assigning to Ty and Tg. This will not synthesize.

I think what you want is to be able to detect a rising edge on "st" and make a decision on that event. The event condition "posedge" is not for that purpose, posedge should be used only for inferring flops.

For st what you want is to detect the rising edge by sampling it with a clock ie:

 

reg st_r;

wire st_posedge = st_r == 0 && st == 1;

always@(posedge clk) begin

  st_r <= st;

  if (value == 5)

    Ty = 1;

  if (st_posedge)

    Ty <= 0;

 

 

This will give you a signal which you can use in your "posedge clk" process to make a decision on how to change Ty & Tg as shown.

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4 Replies
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Scholar
Scholar
4,675 Views
Registered: ‎06-05-2013

Re: Error in Viewing RTL Schematic

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Hello,

I could see you are using signal ty,tg in both the process (always block)
that's why you are getting mentioned error.

you can assign signal ty,tg in only one of the always block. If you want to use in both the always block delcare them as a reg

 

reg ty,tg and use them

Pratham

-Pratham

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Teacher
Teacher
5,813 Views
Registered: ‎03-31-2012

Re: Error in Viewing RTL Schematic

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I think the error is pretty clear. You are assigning to Ty in multiple processes so there are multiple drivers. You have the "posedge clk" process and "posedge st" process which are both assigning to Ty and Tg. This will not synthesize.

I think what you want is to be able to detect a rising edge on "st" and make a decision on that event. The event condition "posedge" is not for that purpose, posedge should be used only for inferring flops.

For st what you want is to detect the rising edge by sampling it with a clock ie:

 

reg st_r;

wire st_posedge = st_r == 0 && st == 1;

always@(posedge clk) begin

  st_r <= st;

  if (value == 5)

    Ty = 1;

  if (st_posedge)

    Ty <= 0;

 

 

This will give you a signal which you can use in your "posedge clk" process to make a decision on how to change Ty & Tg as shown.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post

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4,636 Views
Registered: ‎11-05-2013

Re: Error in Viewing RTL Schematic

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Thank u, ur solution worked :) ... but why doesnt it work when I declare st_posedge as a reg?

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Teacher
Teacher
4,633 Views
Registered: ‎03-31-2012

Re: Error in Viewing RTL Schematic

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This is an idiosyncrasy of Verilog. You can assign to a reg within a process and wire outside a process (generally). If you have a new-ish simulator, it might allow a new type "logic" to which you can assign in either place.
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