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krjasani
Visitor
Visitor
839 Views
Registered: ‎05-20-2019

FDCP cannot be timed accurately Critical warning in Ultrascale Device

Hello,

I am getting following critical warning during synthesis 

[Netlist 29-358] Reg 'Shadow_reg' of type 'FDCP' cannot be timed accurately. Hardware behavior may be unpredictable. Use check_timing command for more information. [

The RTL is as follows :

always @(posedge DCLK  or negedge Brd_Reset_B) begin
  if (Brd_Reset_B) begin
       Shadow2D<=MODE & SDI;
           if (MODE) begin
             SDO<=SDI;
                if (~SDI)
                  Shadow<=Y;
          end

          else begin //Serial shift
             SDO<=Shadow[7];
            Shadow[7]<=Shadow[6];
            Shadow[6]<=Shadow[5];
            Shadow[5]<=Shadow[4];
            Shadow[4]<=Shadow[3];
           Shadow[3]<=Shadow[2];
           Shadow[2]<=Shadow[1];
           Shadow[1]<=Shadow[0];
          Shadow[0]<=SDI;
          end
       end
 else
   Shadow2D<=0;
end

I am using Vivado 2020.1 and Kintex Ultrascale device.

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15 Replies
apetley
Xilinx Employee
Xilinx Employee
800 Views
Registered: ‎06-14-2018

Hi @krjasani ,

That is because FDCP is inferred using combinational logic, latch and flip-flop.

There are multiple paths in decision making if flop goes in reset or set and these are not deterministic on hardware.

Thanks,

Ajay

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krjasani
Visitor
Visitor
794 Views
Registered: ‎05-20-2019

Hi Ajay,

Can you suggest, how to get rid of this warning as this critical warning shouts while implementing simple D flip flop with async clear.

Regards,

Karan

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avrumw
Expert
Expert
781 Views
Registered: ‎01-23-2009

Whoa.... It took me several minutes to figure out that the polarity of your reset is active low, but your code is testing for the high condition first - in other words, your reset condition is in the "else" portion of the if, and the active part is in the if. While I suppose this should work, I have never seen code done this way, and it threw me (and probably everyone else) off. If you want people to be able to understand your code you probably should code it more conventionally (the asynchronous reset condition first). 

You are also coding two types of flip-flops in the same always block - ones that have asynchronous clear (Shadow2D) and ones that don't (Shadow).

Again, all of this should work, but both aspects are unconventional - try recoding more conventionally - separate the two types of flip-flops in different always blocks and put your reset condition first.

Other than the coding style, there doesn't appear to be anything odd about the Shadow register. It is possible that the tools are getting confused here - your coding style is making this something it isn't. I would look at the elaborated schematic to see what it has created here - I wonder if it isn't a D flip-flop with asynchronous clear, but some kind of latch thing. If so, this would be a tool bug, but it would be one caused by your odd coding style.

Also, what does the check_timing say?

Avrum

drjohnsmith
Teacher
Teacher
767 Views
Registered: ‎07-09-2009

Can I highlight @avrumw comments

Style is everything to redability

 

have look here for how to code a shift register

https://www.allaboutcircuits.com/technical-articles/understanding-verilog-shift-registers/

 

Remember that in FPGAs , all always blocks run at the same time

    so you can , and normally do have many always blocks in the code,

 

Also remember, the tools are great at understanding code,

    but my old teachers used to say there are a few styles that work, and 1001 styles that confuse.

       use the former

dont be afraid to look on line for examples,

    you will see that most are very similar styled.

 

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apetley
Xilinx Employee
Xilinx Employee
757 Views
Registered: ‎06-14-2018

Hi @krjasani ,

I agree with @avrumw , try recoding , separating different types of flops in different always block. Also could you share your complete code. 

Thanks,

Ajay 

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krjasani
Visitor
Visitor
647 Views
Registered: ‎05-20-2019

Hi @apetley,

In the below RTL, I am getting similar critical warning for reg Q1 and Q2.

module Delay3Cycle(
input In_B,
input Reset_B,
input CLK,
output Out,
output Out_B
);

reg Q1,Q2,Q3;

always @(posedge In_B,negedge Reset_B,posedge Q3) begin
if (~Reset_B)
Q1<=1'b1;
else if (Q3)
Q1<=1'b0;
else if (In_B)
else
Q1<=1'b1;
end

always @(posedge CLK,negedge Reset_B,posedge Q3) begin
if (~Reset_B)
Q2<=1'b1;
else begin
if (Q3)
Q2<=1'b0;
else
Q2<=Q1;
end
end

always @(posedge CLK,negedge Reset_B) begin
if (~Reset_B)
Q3<=1'b0;
else begin
Q3<=Q2;
end
end

assign Out=Q3;
assign Out_B=~Q3;
endmodule

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drjohnsmith
Teacher
Teacher
625 Views
Registered: ‎07-09-2009

 

Following is the Verilog code for a flip-flop with a negative-edge clock and asynchronous clear.

module flop (C, D, CLR, Q); 
  input C, D, CLR; 
  output Q; 
  reg Q; 
 
  always @(negedge C or posedge CLR) 
    begin 
      if (CLR) 
        Q = 1'b0; 
      else 
        Q = D; 
    end 
endmodule 

 

Do you notice that C is the clock in this example, and does not occur in the always block code.

where as your using 

always @(posedge In_B,negedge Reset_B,posedge Q3) begin
if (~Reset_B)
Q1<=1'b1;
else if (Q3)
Q1<=1'b0;
else if (In_B)
else
Q1<=1'b1;
end

 

Is In_B a clock or logic .

Sorry , I'm mainly a VHDL now days,   much less ambiguous in VHDL....

Your code just looks "wrong" to me.

 

 

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krjasani
Visitor
Visitor
621 Views
Registered: ‎05-20-2019

Hi @drjohnsmith ,

There was a typo in the code I posted earlier, the actual code doesn't contains "In_B" . Still I am getting critical warning.

 

always @(posedge In_B,negedge Reset_B,posedge Q3) begin
if (~Reset_B)
Q1<=1'b1;
else if (Q3)
Q1<=1'b0;
else
Q1<=1'b1;
end

 

 

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drjohnsmith
Teacher
Teacher
619 Views
Registered: ‎07-09-2009

Im getting feeling that were chasing a moving target here,

may be you could post a file of your code, 

   and an actual verilog expert like @avrumw could help you 

 

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krjasani
Visitor
Visitor
617 Views
Registered: ‎05-20-2019

Hi @drjohnsmith  @avrumw ,

Actual verilog code :

module Delay3Cycle(
    input In_B,
    input Reset_B,
    input CLK,
    output Out,
    output Out_B
    );
    
    reg Q1,Q2,Q3;
    
    always @(posedge In_B,negedge Reset_B,posedge Q3) begin
        if (~Reset_B)
        begin 
            Q1<=1'b1;
        end
         else if (Q3)
         begin
             Q1<=1'b0;
         end
          else  /*if (In_B)*/ begin
             Q1<=1'b1;
             end
    end
    
    always @(posedge CLK,negedge Reset_B,posedge Q3) begin
        if (~Reset_B) 
            Q2<=1'b1;
           else begin
              if (Q3)
                Q2<=1'b0;
               else  
                 Q2<=Q1;
             end
    end
    
    always @(posedge CLK,negedge Reset_B) begin
        if (~Reset_B) 
            Q3<=1'b0;
           else begin
            Q3<=Q2;
         end
    end
    
    assign Out=Q3;
    assign  Out_B=~Q3;
endmodule
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krjasani
Visitor
Visitor
555 Views
Registered: ‎05-20-2019

Hi @drjohnsmith  @avrumw ,

When I change device from Kintex Ultrascale to Virtex-7 or Artrix, that critical warning vanished.

Is there issue with kintex ultrascale devices only ?

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avrumw
Expert
Expert
529 Views
Registered: ‎01-23-2009

These new code pieces aren't anything like the old one. You should stick to one issue at a time.

But they all boil down to one thing. You need to code your flip-flops like flip-flops. The flip-flops in Xilinx FPGAs have any ONE of

  • asynchronous preset
  • asynchronous clear
  • synchronous set
  • synchronous reset

A synchronous set/reset can be mapped to logic in front of the D input of the flop, but an asynchronous preset/clear cannot. Some of your code snippets are trying to infer a flip flop with both an asynchronous preset and an asynchronous clear - there is no such cell in the FPGA library, so the tool is building "something else" - probably a flip-flop with a latch around it. Latches are to be avoided...

Furthermore, why would you have the asynchronous preset/clear of one flip-flop driven by another flip-flop? I can see very little reason for doing this.

You need to go back to synchronous digital design basics. All flip-flops should be driven on one edge of the clock only, and, generally, asynchronous preset/clear inputs (if used at all) should not be used for "functional" logic - they should only be used to implement global asynchronous resets (through a reset bridge or other synchronizer). What you are doing here doesn't look like that.

Avrum

krjasani
Visitor
Visitor
514 Views
Registered: ‎05-20-2019

Hi, Thanks for response.

But tool should shout the similar warning when I use virtex or artix device.

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TimKing
Newbie
Newbie
512 Views
Registered: ‎04-14-2021

Thank you ! You gave me the answer in another task )))

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drjohnsmith
Teacher
Teacher
494 Views
Registered: ‎07-09-2009

Just a note, in case this sort of thing happens

   You should have seen latches being created warnings in the log windows,

If yo ever see something strange, its always best to look in the log files first, and see you understand the warnings.

   Latches can not be timed 

 

 

 

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