09-25-2013 01:36 AM
hello every one
please assist me in following as question says...
I have receivedFF/latch trimming message even after 'Equivalent Register Removal' deassertion...What to do
the thing is that my signal is multiplying by 4, what ever the value, so hence it has LSB 2 bits always '0'...but the XST categorically regect to synthesize it as a logic...Hence I think this will ultimately change the design as well...please see warning (infact error) and and code below
signal sig_levels : integer range 0 to 1023; process(clk) begin ... ... ... --rising_edge ... if(xxx) then sig_levels <= siga * sigb * 4; end if; end process; ... ...
09-25-2013 01:44 AM
This is not equivalent register removal. So disabling equivalent register removal does not make any difference here.
As I can see, this is correct trimming since the LSB 2 bits are always 0. Why do you think this will cause problem in your design? Do you see any incorrect function in post-synthesis simulation?
09-25-2013 01:51 AM
no the thing is it will make my whole logic wrong...
as I have shown that my signal is multiplying by a CONSTANT '4'...hence it will definitley have 00 at teh 2 LSB positions...
but trimming it off would mean my logic would be entirely negated... i.e.
in place of XY_plane = 1600 I would be having XY_plane = 400 which is of course wrong...
any suggestion (except for changing the whole logic ^_^)
09-25-2013 04:10 AM
sraza, your understanding of logic trimming is incorrect. Only redundant logic has been removed.
-- Bob Elkind