cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
sraza
Explorer
Explorer
3,960 Views
Registered: ‎03-13-2012

FF/latch trimming message even after 'Equivalent Register Removal' deassertion

 

hello every one

 

please assist me in following as question says...

 

I have receivedFF/latch trimming message even after 'Equivalent Register Removal' deassertion...What to do

the thing is that my signal is multiplying by 4, what ever the value, so hence it has LSB 2 bits always '0'...but the XST categorically regect to synthesize it as a logic...Hence I think this will ultimately change the design as well...please see warning (infact error) and  and code below

 

WARNING:Xst:1293 - FF/Latch <XY_plane_1> has a constant value of 0 in block <Inst_dout_module>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <XY_plane_0> has a constant value of 0 in block <Inst_dout_module>. This FF/Latch will be trimmed during the optimization process.

 

 

signal sig_levels : integer range 0 to 1023;

process(clk)
begin
...
...
...
--rising_edge
...
if(xxx) then
 sig_levels <= siga * sigb * 4;
end if;

end process;
...
...

 

 

Tags (1)
0 Kudos
Reply
3 Replies
viviany
Xilinx Employee
Xilinx Employee
3,957 Views
Registered: ‎05-14-2008

This is not equivalent register removal. So disabling equivalent register removal does not make any difference here.

 

As I can see, this is correct trimming since the LSB 2 bits are always 0. Why do you think this will cause problem in your design? Do you see any incorrect function in post-synthesis simulation?

 

Thanks

Vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos
Reply
sraza
Explorer
Explorer
3,953 Views
Registered: ‎03-13-2012

no the thing is it will make my whole logic wrong...

 

as I have shown that my signal is multiplying by a CONSTANT '4'...hence it will definitley have 00 at teh 2 LSB positions...

 

but trimming it off would mean my logic would be entirely negated... i.e.

 

in place of XY_plane = 1600  I would be having XY_plane = 400  which is of course wrong...

 

any suggestion (except for changing the whole logic ^_^)

0 Kudos
Reply
eteam00
Instructor
Instructor
3,939 Views
Registered: ‎07-21-2009

sraza, your understanding of logic trimming is incorrect.  Only redundant logic has been removed.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Reply