07-23-2018 11:45 AM
Previously, I use VIVADO-2017.1 to synthesize the ARM cortex-R5 and DAPLITE. Everything is fine. For some reason, I have to move on to VIVADO-2018.1. So, i use exactly same code base with constrains ant TCL, but the bitfile from 2018.1 is not working. After debugging the SCH, VIVADO-2018.1 remove lots of lots module as the following figure.
Then, we study the rumme.log and then find the difference for the FSM extraction between 2018.1 and 2017.1
2017.1 synthesize rumme.log
2018.1 synthesize rumme.log
So, the problem is the 2018.1 and 2017.1 have different strategy for the FSM extraction. Moreover, I also try different option for the 2018.1 FSM extraction, but always get same result. In a words, 2017.1 is OK, but 2018.1 is not.
I attached the both synth runme.log. pls check. thanks
07-24-2018 05:10 AM
Can you try manually extracting the FSM by using FSM_ENCODING attribute in RTL and let us know if that helps to proceed further?
Also, as mentioned by Manusha please share a test case for us to reproduce the issue at our end.
07-24-2018 02:30 PM
Sorry. I could not send the file to xilinx. Just paste the state-machine here. Please check it. thanks
08-28-2018 08:00 PM