cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer
Observer
5,335 Views
Registered: ‎03-02-2015

FSM extraction with multiple FSMs in one SystemVerilog module

I noticed recently that if you have two FSMs in one module, synthesis only extracts the first one.  I found this out because, while working on the design, I noticed that it wasn't ever extracting the second FSM in the module. When I experimented with recoding the first FSM as explicit one-hot using a coding style that defeats Vivado's FSM extraction, suddenly the second FSM started getting extracted. Backed out the experiment (so both FSMs were once again coded in the same style) and it returned to extracting the first FSM and ignoring the second.

 

It's not a real problem but I was wondering if this was known and/or intended behavior? Seems like it must be the FSM extraction code assuming it's done after finding a FSM instead of scanning for more of them.

 

It does cause one slight annoyance. I'm using SV enums for FSM states:

enum { STATE1, STATE2, STATE3 } state, next_state;
always_ff @(posedge clk)
    if (reset) state <= STATE1;
    else       state <= next_state;
/* ... */

As written, state/next_state are 32-bit variables. If the FSM gets extracted, these are modified to just enough bits to encode all the states. If the FSM isn't extracted, you get a ton of WARNINGs about optimizing away the unused flops inferred from the 'state' variable.

 

0 Kudos
1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
5,298 Views
Registered: ‎08-01-2008

Re: FSM extraction with multiple FSMs in one SystemVerilog module

check the synthesis property

This is one related ARs . It may be help you

http://www.xilinx.com/support/answers/52307.html
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos