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condo

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12-12-2018 10:24 AM

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Registered:
12-12-2018

FSM in VHDL is Moore or Mealy?

I am coding a FSM in VHDL. In particular it is a synchronized sequence detector that has in input a number on 8 bit and a "first", that has to be '1' only during the first number of the sequence. The output is composed by an unlock and warning: unlock = '1' if the sequence (36, 19, 56, 101, 73) was right, or warning = '1' if the sequence was wrong or first = '1' not during the first number of the sequence.

In VHDL I use two processes, one synchronized and one not. The simplified version of the second is:

combinatorial_logic_p : process(current_state, num_in, first) begin unlock <= '0'; warning <= '0'; case (current_state) is when S0 => if (to_integer(unsigned(num_in)) = 36) and (first = '1') then next_state <= S1; else next_state <= S0; when S1 =>

--........

when S4 =>

correct <= '0';

if (to_integer(unsigned(num_in)) = 73) and (first = '0') and (to_integer(unsigned(five_cycles)) = 5) then

next_state <= S5;

correct <= '1';

elsif first = '1' then

next_state <= S6;

else

next_state <= S0;

end if; end case; end process combinatorial_logic_p;

By reading online I know that in a Moore machine the next state depends on the current state only so the outputs only change on clock edges, while in Mealy it depends also on the input so its outputs may change when an input changes (i.e., not necessarily on a clock edge). .

In my sensitivity list I use current_state and 2 inputs (num_in and first), so is it possible to say that I am describing a Mealy machine or is it still a Moore machine because I am waiting the next rising edge to update the output?

I still think it is Moore, but I am not sure. Thanks

4 Replies

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kinkeads

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12-12-2018 11:15 AM

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Registered:
12-20-2010

Re: FSM in VHDL is Moore or Mealy?

Mealy or Moore depends on how you code your outputs. I only see one output, "correct", in your sample code below. It is driven by combinatorial logic that depends on the current state and the inputs. The output can change as soon as the inputs change, regardless of the clock, so that output is type Mealy.

It is possible to code additional outputs to be synchronous to the clock and depend purely on the current state. Those outputs would be Moore. In other words, you can have a mix of Moore and Mealy outputs in one state machine.

Moore outputs are synchronous, so are less likely to glitch and create unexpected results.

Mealy outputs respond sooner, so use them when latency is important.

condo

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12-12-2018 11:24 AM

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12-12-2018

Re: FSM in VHDL is Moore or Mealy?

Thanks @kinkeads, so I will add the whole code to explain better my doubts:

library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity secure_seq is generic (N : positive := 8); port ( num_in : in std_logic_vector(N - 1 downto 0); first : in std_logic; rst : in std_logic; clk : in std_logic; warning : out std_logic; unlock : out std_logic ); end secure_seq; architecture fsm of secure_seq is type state is (S0, S1, S2, S3, S4, S5, S6); -------------------------------------------------------------- -- Signals declaration -------------------------------------------------------------- signal current_state : state := S0; signal next_state : state ;--:= S0; signal correct : std_logic := '0'; signal first_error : std_logic := '1'; signal five_cycles : unsigned(2 downto 0) := "000";--"001"; signal errors_num : unsigned(1 downto 0) := "00"; begin state_register_p : process(clk)--(rst, clk) begin if (clk'EVENT and clk = '1') then if(rst = '0') then current_state <= S0; errors_num <= "00"; five_cycles <= "000";--"001"; first_error <= '1'; else current_state <= next_state; if to_integer(unsigned(five_cycles)) = 1 then first_error <= '0'; end if; five_cycles <= five_cycles + "001"; if to_integer(unsigned(five_cycles)) = 5 then five_cycles <= "001"; if correct = '0' then --or first_error = '1' then errors_num <= errors_num + "01"; else errors_num <= "00"; end if; end if; end if; end if; end process state_register_p; output_logic_p : process(current_state, num_in, first, five_cycles, correct, first_error, errors_num) begin unlock <= '0'; warning <= '0'; case (current_state) is when S0 => correct <= '0'; if (to_integer(unsigned(num_in)) = 36) and (first = '1') and (to_integer(unsigned(five_cycles)) = 1) and errors_num /= "11" then next_state <= S1; elsif (to_integer(unsigned(num_in)) /= 36) and (first = '1') and (to_integer(unsigned(five_cycles)) = 1) and errors_num /= "11" then next_state <= S0; elsif errors_num = "11" or ((first = '1') and (to_integer(unsigned(five_cycles)) /= 1)) then next_state <= S6; elsif errors_num < "11" then next_state <= S0; else next_state <= S0; end if; if to_integer(unsigned(five_cycles)) = 1 and correct = '0' and first_error /= '1' then warning <= '1'; end if; when S1 => correct <= '0'; if (to_integer(unsigned(num_in)) = 19) and (first = '0') and errors_num /= "11" then next_state <= S2; elsif first = '1' or errors_num = "11" then next_state <= S6; else next_state <= S0; end if; when S2 => correct <= '0'; if (to_integer(unsigned(num_in)) = 56) and (first = '0') then next_state <= S3; elsif first = '1' then next_state <= S6; else next_state <= S0; end if; when S3 => correct <= '0'; if (to_integer(unsigned(num_in)) = 101) and (first = '0') then next_state <= S4; elsif first = '1' then next_state <= S6; else next_state <= S0; end if; when S4 => correct <= '0'; if (to_integer(unsigned(num_in)) = 73) and (first = '0') and (to_integer(unsigned(five_cycles)) = 5) then next_state <= S5; correct <= '1'; elsif first = '1' then next_state <= S6; else next_state <= S0; end if; when S5 => correct <= '1'; if to_integer(unsigned(num_in)) = 36 and (first = '1') then next_state <= S1; else next_state <= S0; end if; unlock <= '1'; when S6 => correct <= '0'; next_state <= S6; -- default, hold in current state warning <= '1'; --when others => end case; end process output_logic_p; end fsm;

So correct is an internal signal, while warning and unlock are my output signals. These outputs are immediately updated, so it seems to be Mealy, but I see the output value changing at the same time of the rising edge of the clock, so it seems to be "synchronous". Is it still Mealy now with the entire code? Thanks

kinkeads

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12-12-2018 11:45 AM

802 Views

Registered:
12-20-2010

Re: FSM in VHDL is Moore or Mealy?

The signals "warning" and "unlock" are driven by combinatorial logic, but their state depends only on the register "current_state", so I consider them to be of type Moore. Toggling the inputs "first" and "num_in" will not cause an immediate change in "warning" or "unlock".

Even so, it would be good practice to pass "warning" and "unlock" through a flip-flop to drive the output ports of the secure_seq module, assuming the additional clock delay is acceptable.

condo

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12-12-2018 11:53 AM

796 Views

Registered:
12-12-2018

Re: FSM in VHDL is Moore or Mealy?