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Visitor abdn
Visitor
8,992 Views
Registered: ‎05-03-2011

FSM synthesis

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hi all.

 

when i synthesize the following code it give error..

 

code:

 

 
module FSM(t,ack,c_ack,state);
input t,ack,c_ack;
output reg [3:0]state;
 parameter [3:0]RUN     =4'b0001;
 parameter [3:0]COMPARE =4'b0100;
 parameter [3:0]CLR	   =4'b1010;
 
 always @ (posedge t or posedge ack or posedge c_ack)
  begin  
  case(state)
  RUN     :state<=COMPARE;
  COMPARE :state<=CLR;
  CLR     :state<=RUN;
  default :state<=RUN;
  endcase
  end
endmodule

 

synthesis of this code generate following error message.

 

ERROR: The logic for <state> does not match a known FF or Latch template.

 

 

wht is problem with the code????

 

 

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Visitor abdn
Visitor
11,318 Views
Registered: ‎05-03-2011

Re: FSM synthesis

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wrote:

 

The synthesizer doesn't know what you want and I don't either..

------------------------------------------------------------------------------------

what i want is to:

  • change state when posedge of any input occurs....

purpose of the FSM:

i have a circuit with 4 blocks(named as A,B,C,D).. this fsm is meant to controls that 4 blocks..

  • it disable and enable blocks...(state[0] is enable for block A,state[1] is enable for block B and so on )
  • block A,B&C generate an acknowledgement when they perform their task each of which is input to FSM(t,ack,c_ack).
  • based on these acknowledgements FSM generate output......

About blocks(A,B,C,D):

  1. at start block A runs and when perform its task assert " t "..
  2. then FSM enables block B... when it perform its task it assert "ack".
  3. then FSM enable block C & D. . when block C perform its task it asserts "c_ack"
  4. then FSM enables block  A and goto step 1...
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12 Replies
Xilinx Employee
Xilinx Employee
8,988 Views
Registered: ‎01-03-2008

Re: FSM synthesis

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You have three posedge qualifiers for the always block that you don't use in the process and the one variable that is used isn't in the sensitivity list.

The synthesizer doesn't know what you want and I don't either.
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Advisor evgenis1
Advisor
8,986 Views
Registered: ‎12-03-2007

Re: FSM synthesis

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Hi,

 

Here is an overview of different state machine coding styles for synthesis: 

   http://www.xilinx.com/itp/xilinx4/data/docs/xst/hdlcode15.html

 

 

As the error message suggests, the logic for <state> does not match a known FF or Latch template.

Your code doesn't have neither clock nor latch enable.

 

Thanks,

Evgeni

 

 

 

Tags (1)
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Visitor abdn
Visitor
11,319 Views
Registered: ‎05-03-2011

Re: FSM synthesis

Jump to solution

wrote:

 

The synthesizer doesn't know what you want and I don't either..

------------------------------------------------------------------------------------

what i want is to:

  • change state when posedge of any input occurs....

purpose of the FSM:

i have a circuit with 4 blocks(named as A,B,C,D).. this fsm is meant to controls that 4 blocks..

  • it disable and enable blocks...(state[0] is enable for block A,state[1] is enable for block B and so on )
  • block A,B&C generate an acknowledgement when they perform their task each of which is input to FSM(t,ack,c_ack).
  • based on these acknowledgements FSM generate output......

About blocks(A,B,C,D):

  1. at start block A runs and when perform its task assert " t "..
  2. then FSM enables block B... when it perform its task it assert "ack".
  3. then FSM enable block C & D. . when block C perform its task it asserts "c_ack"
  4. then FSM enables block  A and goto step 1...
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Visitor abdn
Visitor
8,977 Views
Registered: ‎05-03-2011

Re: FSM synthesis

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@avgenis:

 thanks ... i am reading the material ........ it will help alot..

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Teacher eteam00
Teacher
8,967 Views
Registered: ‎07-21-2009

Re: FSM synthesis

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change state when posedge of any input occurs....

 

There is no physical hardware construct which performs this function for more than one input -- a clock.  Even an asynchronous set/reset doesn't qualify, as this type of input is level-sensitive rather than edge-sensitive.

 

If this is a school project, it's a good one.  It forces you to implement a function which does not map directly to simple hardware.  You will need to build this sort of function from combinatorial logic and clocked registers.  This is a valuable lesson to learn.

 

If this is a school assignment, this forum should give you a chance to work through the assignment rather than doing your homework for you.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Visitor abdn
Visitor
8,960 Views
Registered: ‎05-03-2011

Re: FSM synthesis

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thank u all for replies.....

.

i was not aware of the fact that such latch does not exist...

i found way to convert that 3 inputs into 1 input and now i am using that input as clock to FSM...

now it works..

 

 

 

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Historian
Historian
8,936 Views
Registered: ‎02-25-2008

Re: FSM synthesis

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@abdn wrote:

thank u all for replies.....

.

i was not aware of the fact that such latch does not exist...

i found way to convert that 3 inputs into 1 input and now i am using that input as clock to FSM...

now it works..

 

 


Hah, not for long will it work ...

----------------------------Yes, I do this for a living.
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Teacher eteam00
Teacher
8,933 Views
Registered: ‎07-21-2009

Re: FSM synthesis

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i found way to convert that 3 inputs into 1 input and now i am using that input as clock to FSM...

 

When you first posted this, I didn't catch the highlighted phrase.

Bassman's ominous warning drew my attention.

 

This approach usually leads to unsolvable problems.  Has your instructor covered the differences between asynchronous design and synchronous design?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor abdn
Visitor
8,924 Views
Registered: ‎05-03-2011

Re: FSM synthesis

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@bob

 

ok i throw away my former thought and Now i modified my code as follows....

module FSM(clk,ackCM,ackCT,state);
input clk;				
input ackCM;				//from CPTR
input ackCT;                            //from CR               
output reg [2:0]state;		 				
reg [2:0]next_state;                      
reg [29:0]count=0;	

 parameter [2:0]RUN     =3'b001;//generate adress  
 parameter [2:0]COMPARE =3'b010;//in this state CPTR do its job...
 parameter [2:0]CLR	=3'b100;//in this state CR do its job...
 
 always @ (posedge clk)begin
    state<=next_state;		//update state
     if(state[0])count<=count+1;//counting is done only in RUN state..
	 else count<=0; 	//clear counter in other states..
 end
 
 always @ *
  begin  
  case(state)
  RUN    :if(count<=50000000) next_state=state; //OS RUNs for 1 sec..
	   else next_state=COMPARE; //after 1 sec cpr come into action.	
 COMPARE:if(ackCM) next_state=CLR; //if cpr is over SR and CR-
	else next_state=state;	    //take charge.
  CLR   :if(ackCT) next_state=RUN; //after they r finished again OSstrt	
				else next_state=state;
 default :next_state=RUN;
  endcase
  end
endmodule

 i think now it is synchronous... is it?

 

 

@bassman59

  thanks for your kind reply....

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Teacher eteam00
Teacher
4,523 Views
Registered: ‎07-21-2009

Re: FSM synthesis

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1.  It looks quite synchronous to me.

 

2.  I prefer single-process state machine to 2-process state machine.  Nothing in your design suggests you need 2 processes.

 

3. Your code would be more 'clean' if the first IF statement is written if(state == RUN).  If you use parameters and named states, you should be consistent in their use.

 

4.  Make sure the ackCM and ackCT inputs are synchronised to clk, otherwise you will have lockup problems.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Visitor abdn
Visitor
4,511 Views
Registered: ‎05-03-2011

Re: FSM synthesis

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thanks bob...

 

i'll act upon your advice(2,3)...

 

i am new to verilog and ISE that is why i am asking more questions.. and also i have no one near by who could help me nor i have enough resources except a  "low speed internet connection"....

 

        you really help me and put me on right way...

 

     giving time to others in this busy life is difficult... i really appreciate you

 

  My English is not good .. sorry for mistakes....

 

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Teacher eteam00
Teacher
4,500 Views
Registered: ‎07-21-2009

Re: FSM synthesis

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i'll act upon your advice(2,3)...

 

Don't forget #4.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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