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Observer dck140130
Observer
639 Views
Registered: ‎02-06-2018

Failed Synthesis, and Elaboration for recursive function call in Vivado 2017.4

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Hello,

What you will find attached is atypical in many ways. There is no explicit timing other than an always sensitivity list in the top module that calls a function that calls many other functions, a couple of which are recursive. I want this to be an asynchronous pipeline of functions.

You will find the automatic keyword on the recursive functions.
I have not attempted to recode using generate blocks as is found here (http://jad-reads.blogspot.com/2009/03/recursive-and-iterative-designs-in.html)

I have tried using the following command found in the Vivado User guide:  " -recursion_iteration_limit 2" ,

pg 222 https://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_3/ug901-vivado-synthesis.pdf

The errors are only that synthesis fails. Synthesis attempt uses 16 gb of ram. Please feel free to use one of the non recursive functions found in the header file to realize that elaboration is possible and synthesis still fails due to lack of IO constraints.

 The header file "fibhead.vh" is not attached because forum will not allow me attach if not in .v. I have changed the file to .v and it is still not letting me attach.I have replied twice to this post with all of the functions that belong in the header file.

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Scholar markcurry
Scholar
317 Views
Registered: ‎09-16-2009

Re: Failed Synthesis, and Elaboration for recursive function call in Vivado 2017.4/2018.3

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To be fair, I wasn't aware of the "recursion_iteration_limit" argument, nor do I really understand what the switch would do.

I tried my example "fact1" above, with something that required more than 64 depth recursion.  It's still worked fine.  Although I didn't check if the result of 66! was accurate - that's a big number - would require 309 bits  - although the function as written only keeps the lower 8.

So I'm not sure wat that switch is doing. Perhaps in other recursive cases  - factorial is a bad example - where there's variable, and constant arguments.  The constant arguments could be used by the tool to determine recursion depth, but the variable arguments would affect the function? (total guess on my part).  Maybe in those instances, the tool's limited to "recursion_iteration_limit" depths?  I dunno.  I'd play around with other recursive functions perhaps to shed some light here, if you're curious and have need.

In any event, for the examples I provided - the only one that works "fact1.v" produces no logic at all.  The result is a constant - all the output ports will just be tied off 1 or 0.

Regards,

Mark

10 Replies
Observer dck140130
Observer
629 Views
Registered: ‎02-06-2018

Re: Failed Synthesis, and Elaboration for recursive function call in Vivado 2017.4

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function [1:0] cmp_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: cmp_0_lut = 2'b01;
6'b011111: cmp_0_lut = 2'b10;
6'b101111: cmp_0_lut = 2'b10;
6'b110111: cmp_0_lut = 2'b11;
6'b010111: cmp_0_lut = 2'b01;
6'b100111: cmp_0_lut = 2'b10;
6'b111011: cmp_0_lut = 2'b11;
6'b011011: cmp_0_lut = 2'b11;
6'b101011: cmp_0_lut = 2'b01;
6'b111101: cmp_0_lut = 2'b01;
6'b011101: cmp_0_lut = 2'b10;
6'b101101: cmp_0_lut = 2'b10;
6'b110101: cmp_0_lut = 2'b11;
6'b010101: cmp_0_lut = 2'b01;
6'b100101: cmp_0_lut = 2'b10;
6'b111001: cmp_0_lut = 2'b11;
6'b011001: cmp_0_lut = 2'b11;
6'b101001: cmp_0_lut = 2'b01;
6'b111110: cmp_0_lut = 2'b01;
6'b011110: cmp_0_lut = 2'b10;
6'b101110: cmp_0_lut = 2'b10;
6'b110110: cmp_0_lut = 2'b11;
6'b010110: cmp_0_lut = 2'b01;
6'b100110: cmp_0_lut = 2'b10;
6'b111010: cmp_0_lut = 2'b11;
6'b011010: cmp_0_lut = 2'b11;
6'b101010: cmp_0_lut = 2'b01;
default: cmp_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] isLess_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: isLess_0_lut = 2'b10;
6'b011111: isLess_0_lut = 2'b11;
6'b101111: isLess_0_lut = 2'b11;
6'b110111: isLess_0_lut = 2'b10;
6'b010111: isLess_0_lut = 2'b11;
6'b100111: isLess_0_lut = 2'b11;
6'b111011: isLess_0_lut = 2'b10;
6'b011011: isLess_0_lut = 2'b11;
6'b101011: isLess_0_lut = 2'b11;
6'b111101: isLess_0_lut = 2'b10;
6'b011101: isLess_0_lut = 2'b11;
6'b101101: isLess_0_lut = 2'b11;
6'b110101: isLess_0_lut = 2'b10;
6'b010101: isLess_0_lut = 2'b11;
6'b100101: isLess_0_lut = 2'b11;
6'b111001: isLess_0_lut = 2'b10;
6'b011001: isLess_0_lut = 2'b11;
6'b101001: isLess_0_lut = 2'b11;
6'b111110: isLess_0_lut = 2'b10;
6'b011110: isLess_0_lut = 2'b11;
6'b101110: isLess_0_lut = 2'b11;
6'b110110: isLess_0_lut = 2'b10;
6'b010110: isLess_0_lut = 2'b11;
6'b100110: isLess_0_lut = 2'b11;
6'b111010: isLess_0_lut = 2'b10;
6'b011010: isLess_0_lut = 2'b11;
6'b101010: isLess_0_lut = 2'b11;
default: isLess_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] isGreater_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: isGreater_0_lut = 2'b11;
6'b011111: isGreater_0_lut = 2'b11;
6'b101111: isGreater_0_lut = 2'b10;
6'b110111: isGreater_0_lut = 2'b11;
6'b010111: isGreater_0_lut = 2'b11;
6'b100111: isGreater_0_lut = 2'b10;
6'b111011: isGreater_0_lut = 2'b11;
6'b011011: isGreater_0_lut = 2'b11;
6'b101011: isGreater_0_lut = 2'b10;
6'b111101: isGreater_0_lut = 2'b11;
6'b011101: isGreater_0_lut = 2'b11;
6'b101101: isGreater_0_lut = 2'b10;
6'b110101: isGreater_0_lut = 2'b11;
6'b010101: isGreater_0_lut = 2'b11;
6'b100101: isGreater_0_lut = 2'b10;
6'b111001: isGreater_0_lut = 2'b11;
6'b011001: isGreater_0_lut = 2'b11;
6'b101001: isGreater_0_lut = 2'b10;
6'b111110: isGreater_0_lut = 2'b11;
6'b011110: isGreater_0_lut = 2'b11;
6'b101110: isGreater_0_lut = 2'b10;
6'b110110: isGreater_0_lut = 2'b11;
6'b010110: isGreater_0_lut = 2'b11;
6'b100110: isGreater_0_lut = 2'b10;
6'b111010: isGreater_0_lut = 2'b11;
6'b011010: isGreater_0_lut = 2'b11;
6'b101010: isGreater_0_lut = 2'b10;
default: isGreater_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] isEqual_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: isEqual_0_lut = 2'b11;
6'b011111: isEqual_0_lut = 2'b10;
6'b101111: isEqual_0_lut = 2'b11;
6'b110111: isEqual_0_lut = 2'b11;
6'b010111: isEqual_0_lut = 2'b10;
6'b100111: isEqual_0_lut = 2'b11;
6'b111011: isEqual_0_lut = 2'b11;
6'b011011: isEqual_0_lut = 2'b10;
6'b101011: isEqual_0_lut = 2'b11;
6'b111101: isEqual_0_lut = 2'b11;
6'b011101: isEqual_0_lut = 2'b10;
6'b101101: isEqual_0_lut = 2'b11;
6'b110101: isEqual_0_lut = 2'b11;
6'b010101: isEqual_0_lut = 2'b10;
6'b100101: isEqual_0_lut = 2'b11;
6'b111001: isEqual_0_lut = 2'b11;
6'b011001: isEqual_0_lut = 2'b10;
6'b101001: isEqual_0_lut = 2'b11;
6'b111110: isEqual_0_lut = 2'b11;
6'b011110: isEqual_0_lut = 2'b10;
6'b101110: isEqual_0_lut = 2'b11;
6'b110110: isEqual_0_lut = 2'b11;
6'b010110: isEqual_0_lut = 2'b10;
6'b100110: isEqual_0_lut = 2'b11;
6'b111010: isEqual_0_lut = 2'b11;
6'b011010: isEqual_0_lut = 2'b10;
6'b101010: isEqual_0_lut = 2'b11;
default: isEqual_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] notLess_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: notLess_0_lut = 2'b11;
6'b011111: notLess_0_lut = 2'b10;
6'b101111: notLess_0_lut = 2'b10;
6'b110111: notLess_0_lut = 2'b11;
6'b010111: notLess_0_lut = 2'b10;
6'b100111: notLess_0_lut = 2'b10;
6'b111011: notLess_0_lut = 2'b11;
6'b011011: notLess_0_lut = 2'b10;
6'b101011: notLess_0_lut = 2'b10;
6'b111101: notLess_0_lut = 2'b11;
6'b011101: notLess_0_lut = 2'b10;
6'b101101: notLess_0_lut = 2'b10;
6'b110101: notLess_0_lut = 2'b11;
6'b010101: notLess_0_lut = 2'b10;
6'b100101: notLess_0_lut = 2'b10;
6'b111001: notLess_0_lut = 2'b11;
6'b011001: notLess_0_lut = 2'b10;
6'b101001: notLess_0_lut = 2'b10;
6'b111110: notLess_0_lut = 2'b11;
6'b011110: notLess_0_lut = 2'b10;
6'b101110: notLess_0_lut = 2'b10;
6'b110110: notLess_0_lut = 2'b11;
6'b010110: notLess_0_lut = 2'b10;
6'b100110: notLess_0_lut = 2'b10;
6'b111010: notLess_0_lut = 2'b11;
6'b011010: notLess_0_lut = 2'b10;
6'b101010: notLess_0_lut = 2'b10;
default: notLess_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] notGreater_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: notGreater_0_lut = 2'b10;
6'b011111: notGreater_0_lut = 2'b10;
6'b101111: notGreater_0_lut = 2'b11;
6'b110111: notGreater_0_lut = 2'b10;
6'b010111: notGreater_0_lut = 2'b10;
6'b100111: notGreater_0_lut = 2'b11;
6'b111011: notGreater_0_lut = 2'b10;
6'b011011: notGreater_0_lut = 2'b10;
6'b101011: notGreater_0_lut = 2'b11;
6'b111101: notGreater_0_lut = 2'b10;
6'b011101: notGreater_0_lut = 2'b10;
6'b101101: notGreater_0_lut = 2'b11;
6'b110101: notGreater_0_lut = 2'b10;
6'b010101: notGreater_0_lut = 2'b10;
6'b100101: notGreater_0_lut = 2'b11;
6'b111001: notGreater_0_lut = 2'b10;
6'b011001: notGreater_0_lut = 2'b10;
6'b101001: notGreater_0_lut = 2'b11;
6'b111110: notGreater_0_lut = 2'b10;
6'b011110: notGreater_0_lut = 2'b10;
6'b101110: notGreater_0_lut = 2'b11;
6'b110110: notGreater_0_lut = 2'b10;
6'b010110: notGreater_0_lut = 2'b10;
6'b100110: notGreater_0_lut = 2'b11;
6'b111010: notGreater_0_lut = 2'b10;
6'b011010: notGreater_0_lut = 2'b10;
6'b101010: notGreater_0_lut = 2'b11;
default: notGreater_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] notEqual_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: notEqual_0_lut = 2'b10;
6'b011111: notEqual_0_lut = 2'b11;
6'b101111: notEqual_0_lut = 2'b10;
6'b110111: notEqual_0_lut = 2'b10;
6'b010111: notEqual_0_lut = 2'b11;
6'b100111: notEqual_0_lut = 2'b10;
6'b111011: notEqual_0_lut = 2'b10;
6'b011011: notEqual_0_lut = 2'b11;
6'b101011: notEqual_0_lut = 2'b10;
6'b111101: notEqual_0_lut = 2'b10;
6'b011101: notEqual_0_lut = 2'b11;
6'b101101: notEqual_0_lut = 2'b10;
6'b110101: notEqual_0_lut = 2'b10;
6'b010101: notEqual_0_lut = 2'b11;
6'b100101: notEqual_0_lut = 2'b10;
6'b111001: notEqual_0_lut = 2'b10;
6'b011001: notEqual_0_lut = 2'b11;
6'b101001: notEqual_0_lut = 2'b10;
6'b111110: notEqual_0_lut = 2'b10;
6'b011110: notEqual_0_lut = 2'b11;
6'b101110: notEqual_0_lut = 2'b10;
6'b110110: notEqual_0_lut = 2'b10;
6'b010110: notEqual_0_lut = 2'b11;
6'b100110: notEqual_0_lut = 2'b10;
6'b111010: notEqual_0_lut = 2'b10;
6'b011010: notEqual_0_lut = 2'b11;
6'b101010: notEqual_0_lut = 2'b10;
default: notEqual_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] equal_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: equal_0_lut = 2'b10;
6'b011111: equal_0_lut = 2'b11;
6'b101111: equal_0_lut = 2'b11;
6'b110111: equal_0_lut = 2'b11;
6'b010111: equal_0_lut = 2'b10;
6'b100111: equal_0_lut = 2'b11;
6'b111011: equal_0_lut = 2'b11;
6'b011011: equal_0_lut = 2'b11;
6'b101011: equal_0_lut = 2'b10;
6'b111101: equal_0_lut = 2'b10;
6'b011101: equal_0_lut = 2'b11;
6'b101101: equal_0_lut = 2'b11;
6'b110101: equal_0_lut = 2'b11;
6'b010101: equal_0_lut = 2'b10;
6'b100101: equal_0_lut = 2'b11;
6'b111001: equal_0_lut = 2'b11;
6'b011001: equal_0_lut = 2'b11;
6'b101001: equal_0_lut = 2'b10;
6'b111110: equal_0_lut = 2'b10;
6'b011110: equal_0_lut = 2'b11;
6'b101110: equal_0_lut = 2'b11;
6'b110110: equal_0_lut = 2'b11;
6'b010110: equal_0_lut = 2'b10;
6'b100110: equal_0_lut = 2'b11;
6'b111010: equal_0_lut = 2'b11;
6'b011010: equal_0_lut = 2'b11;
6'b101010: equal_0_lut = 2'b10;
default: equal_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] isMin_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: isMin_0_lut = 2'b10;
6'b011111: isMin_0_lut = 2'b11;
6'b101111: isMin_0_lut = 2'b11;
6'b110111: isMin_0_lut = 2'b10;
6'b010111: isMin_0_lut = 2'b11;
6'b100111: isMin_0_lut = 2'b11;
6'b111011: isMin_0_lut = 2'b10;
6'b011011: isMin_0_lut = 2'b11;
6'b101011: isMin_0_lut = 2'b11;
6'b111101: isMin_0_lut = 2'b10;
6'b011101: isMin_0_lut = 2'b11;
6'b101101: isMin_0_lut = 2'b11;
6'b110101: isMin_0_lut = 2'b10;
6'b010101: isMin_0_lut = 2'b11;
6'b100101: isMin_0_lut = 2'b11;
6'b111001: isMin_0_lut = 2'b10;
6'b011001: isMin_0_lut = 2'b11;
6'b101001: isMin_0_lut = 2'b11;
6'b111110: isMin_0_lut = 2'b10;
6'b011110: isMin_0_lut = 2'b11;
6'b101110: isMin_0_lut = 2'b11;
6'b110110: isMin_0_lut = 2'b10;
6'b010110: isMin_0_lut = 2'b11;
6'b100110: isMin_0_lut = 2'b11;
6'b111010: isMin_0_lut = 2'b10;
6'b011010: isMin_0_lut = 2'b11;
6'b101010: isMin_0_lut = 2'b11;
default: isMin_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] isNegative_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: isNegative_0_lut = 2'b10;
6'b011111: isNegative_0_lut = 2'b11;
6'b101111: isNegative_0_lut = 2'b11;
6'b110111: isNegative_0_lut = 2'b10;
6'b010111: isNegative_0_lut = 2'b11;
6'b100111: isNegative_0_lut = 2'b11;
6'b111011: isNegative_0_lut = 2'b10;
6'b011011: isNegative_0_lut = 2'b11;
6'b101011: isNegative_0_lut = 2'b11;
6'b111101: isNegative_0_lut = 2'b10;
6'b011101: isNegative_0_lut = 2'b11;
6'b101101: isNegative_0_lut = 2'b11;
6'b110101: isNegative_0_lut = 2'b10;
6'b010101: isNegative_0_lut = 2'b11;
6'b100101: isNegative_0_lut = 2'b11;
6'b111001: isNegative_0_lut = 2'b10;
6'b011001: isNegative_0_lut = 2'b11;
6'b101001: isNegative_0_lut = 2'b11;
6'b111110: isNegative_0_lut = 2'b10;
6'b011110: isNegative_0_lut = 2'b11;
6'b101110: isNegative_0_lut = 2'b11;
6'b110110: isNegative_0_lut = 2'b10;
6'b010110: isNegative_0_lut = 2'b11;
6'b100110: isNegative_0_lut = 2'b11;
6'b111010: isNegative_0_lut = 2'b10;
6'b011010: isNegative_0_lut = 2'b11;
6'b101010: isNegative_0_lut = 2'b11;
default: isNegative_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] isOne_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: isOne_0_lut = 2'b11;
6'b011111: isOne_0_lut = 2'b11;
6'b101111: isOne_0_lut = 2'b10;
6'b110111: isOne_0_lut = 2'b11;
6'b010111: isOne_0_lut = 2'b11;
6'b100111: isOne_0_lut = 2'b10;
6'b111011: isOne_0_lut = 2'b11;
6'b011011: isOne_0_lut = 2'b11;
6'b101011: isOne_0_lut = 2'b10;
6'b111101: isOne_0_lut = 2'b11;
6'b011101: isOne_0_lut = 2'b11;
6'b101101: isOne_0_lut = 2'b10;
6'b110101: isOne_0_lut = 2'b11;
6'b010101: isOne_0_lut = 2'b11;
6'b100101: isOne_0_lut = 2'b10;
6'b111001: isOne_0_lut = 2'b11;
6'b011001: isOne_0_lut = 2'b11;
6'b101001: isOne_0_lut = 2'b10;
6'b111110: isOne_0_lut = 2'b11;
6'b011110: isOne_0_lut = 2'b11;
6'b101110: isOne_0_lut = 2'b10;
6'b110110: isOne_0_lut = 2'b11;
6'b010110: isOne_0_lut = 2'b11;
6'b100110: isOne_0_lut = 2'b10;
6'b111010: isOne_0_lut = 2'b11;
6'b011010: isOne_0_lut = 2'b11;
6'b101010: isOne_0_lut = 2'b10;
default: isOne_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] isPositive_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: isPositive_0_lut = 2'b11;
6'b011111: isPositive_0_lut = 2'b11;
6'b101111: isPositive_0_lut = 2'b10;
6'b110111: isPositive_0_lut = 2'b11;
6'b010111: isPositive_0_lut = 2'b11;
6'b100111: isPositive_0_lut = 2'b10;
6'b111011: isPositive_0_lut = 2'b11;
6'b011011: isPositive_0_lut = 2'b11;
6'b101011: isPositive_0_lut = 2'b10;
6'b111101: isPositive_0_lut = 2'b11;
6'b011101: isPositive_0_lut = 2'b11;
6'b101101: isPositive_0_lut = 2'b10;
6'b110101: isPositive_0_lut = 2'b11;
6'b010101: isPositive_0_lut = 2'b11;
6'b100101: isPositive_0_lut = 2'b10;
6'b111001: isPositive_0_lut = 2'b11;
6'b011001: isPositive_0_lut = 2'b11;
6'b101001: isPositive_0_lut = 2'b10;
6'b111110: isPositive_0_lut = 2'b11;
6'b011110: isPositive_0_lut = 2'b11;
6'b101110: isPositive_0_lut = 2'b10;
6'b110110: isPositive_0_lut = 2'b11;
6'b010110: isPositive_0_lut = 2'b11;
6'b100110: isPositive_0_lut = 2'b10;
6'b111010: isPositive_0_lut = 2'b11;
6'b011010: isPositive_0_lut = 2'b11;
6'b101010: isPositive_0_lut = 2'b10;
default: isPositive_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] isZero_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: isZero_0_lut = 2'b11;
6'b011111: isZero_0_lut = 2'b10;
6'b101111: isZero_0_lut = 2'b11;
6'b110111: isZero_0_lut = 2'b11;
6'b010111: isZero_0_lut = 2'b10;
6'b100111: isZero_0_lut = 2'b11;
6'b111011: isZero_0_lut = 2'b11;
6'b011011: isZero_0_lut = 2'b10;
6'b101011: isZero_0_lut = 2'b11;
6'b111101: isZero_0_lut = 2'b11;
6'b011101: isZero_0_lut = 2'b10;
6'b101101: isZero_0_lut = 2'b11;
6'b110101: isZero_0_lut = 2'b11;
6'b010101: isZero_0_lut = 2'b10;
6'b100101: isZero_0_lut = 2'b11;
6'b111001: isZero_0_lut = 2'b11;
6'b011001: isZero_0_lut = 2'b10;
6'b101001: isZero_0_lut = 2'b11;
6'b111110: isZero_0_lut = 2'b11;
6'b011110: isZero_0_lut = 2'b10;
6'b101110: isZero_0_lut = 2'b11;
6'b110110: isZero_0_lut = 2'b11;
6'b010110: isZero_0_lut = 2'b10;
6'b100110: isZero_0_lut = 2'b11;
6'b111010: isZero_0_lut = 2'b11;
6'b011010: isZero_0_lut = 2'b10;
6'b101010: isZero_0_lut = 2'b11;
default: isZero_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] notNegative_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: notNegative_0_lut = 2'b11;
6'b011111: notNegative_0_lut = 2'b10;
6'b101111: notNegative_0_lut = 2'b10;
6'b110111: notNegative_0_lut = 2'b11;
6'b010111: notNegative_0_lut = 2'b10;
6'b100111: notNegative_0_lut = 2'b10;
6'b111011: notNegative_0_lut = 2'b11;
6'b011011: notNegative_0_lut = 2'b10;
6'b101011: notNegative_0_lut = 2'b10;
6'b111101: notNegative_0_lut = 2'b11;
6'b011101: notNegative_0_lut = 2'b10;
6'b101101: notNegative_0_lut = 2'b10;
6'b110101: notNegative_0_lut = 2'b11;
6'b010101: notNegative_0_lut = 2'b10;
6'b100101: notNegative_0_lut = 2'b10;
6'b111001: notNegative_0_lut = 2'b11;
6'b011001: notNegative_0_lut = 2'b10;
6'b101001: notNegative_0_lut = 2'b10;
6'b111110: notNegative_0_lut = 2'b11;
6'b011110: notNegative_0_lut = 2'b10;
6'b101110: notNegative_0_lut = 2'b10;
6'b110110: notNegative_0_lut = 2'b11;
6'b010110: notNegative_0_lut = 2'b10;
6'b100110: notNegative_0_lut = 2'b10;
6'b111010: notNegative_0_lut = 2'b11;
6'b011010: notNegative_0_lut = 2'b10;
6'b101010: notNegative_0_lut = 2'b10;
default: notNegative_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] notPositive_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: notPositive_0_lut = 2'b10;
6'b011111: notPositive_0_lut = 2'b10;
6'b101111: notPositive_0_lut = 2'b11;
6'b110111: notPositive_0_lut = 2'b10;
6'b010111: notPositive_0_lut = 2'b10;
6'b100111: notPositive_0_lut = 2'b11;
6'b111011: notPositive_0_lut = 2'b10;
6'b011011: notPositive_0_lut = 2'b10;
6'b101011: notPositive_0_lut = 2'b11;
6'b111101: notPositive_0_lut = 2'b10;
6'b011101: notPositive_0_lut = 2'b10;
6'b101101: notPositive_0_lut = 2'b11;
6'b110101: notPositive_0_lut = 2'b10;
6'b010101: notPositive_0_lut = 2'b10;
6'b100101: notPositive_0_lut = 2'b11;
6'b111001: notPositive_0_lut = 2'b10;
6'b011001: notPositive_0_lut = 2'b10;
6'b101001: notPositive_0_lut = 2'b11;
6'b111110: notPositive_0_lut = 2'b10;
6'b011110: notPositive_0_lut = 2'b10;
6'b101110: notPositive_0_lut = 2'b11;
6'b110110: notPositive_0_lut = 2'b10;
6'b010110: notPositive_0_lut = 2'b10;
6'b100110: notPositive_0_lut = 2'b11;
6'b111010: notPositive_0_lut = 2'b10;
6'b011010: notPositive_0_lut = 2'b10;
6'b101010: notPositive_0_lut = 2'b11;
default: notPositive_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] notZero_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: notZero_0_lut = 2'b10;
6'b011111: notZero_0_lut = 2'b11;
6'b101111: notZero_0_lut = 2'b10;
6'b110111: notZero_0_lut = 2'b10;
6'b010111: notZero_0_lut = 2'b11;
6'b100111: notZero_0_lut = 2'b10;
6'b111011: notZero_0_lut = 2'b10;
6'b011011: notZero_0_lut = 2'b11;
6'b101011: notZero_0_lut = 2'b10;
6'b111101: notZero_0_lut = 2'b10;
6'b011101: notZero_0_lut = 2'b11;
6'b101101: notZero_0_lut = 2'b10;
6'b110101: notZero_0_lut = 2'b10;
6'b010101: notZero_0_lut = 2'b11;
6'b100101: notZero_0_lut = 2'b10;
6'b111001: notZero_0_lut = 2'b10;
6'b011001: notZero_0_lut = 2'b11;
6'b101001: notZero_0_lut = 2'b10;
6'b111110: notZero_0_lut = 2'b10;
6'b011110: notZero_0_lut = 2'b11;
6'b101110: notZero_0_lut = 2'b10;
6'b110110: notZero_0_lut = 2'b10;
6'b010110: notZero_0_lut = 2'b11;
6'b100110: notZero_0_lut = 2'b10;
6'b111010: notZero_0_lut = 2'b10;
6'b011010: notZero_0_lut = 2'b11;
6'b101010: notZero_0_lut = 2'b10;
default: notZero_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] fullAdd_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: fullAdd_0_lut = 2'b01;
6'b011111: fullAdd_0_lut = 2'b10;
6'b101111: fullAdd_0_lut = 2'b11;
6'b110111: fullAdd_0_lut = 2'b10;
6'b010111: fullAdd_0_lut = 2'b11;
6'b100111: fullAdd_0_lut = 2'b01;
6'b111011: fullAdd_0_lut = 2'b11;
6'b011011: fullAdd_0_lut = 2'b01;
6'b101011: fullAdd_0_lut = 2'b10;
6'b111101: fullAdd_0_lut = 2'b10;
6'b011101: fullAdd_0_lut = 2'b11;
6'b101101: fullAdd_0_lut = 2'b01;
6'b110101: fullAdd_0_lut = 2'b11;
6'b010101: fullAdd_0_lut = 2'b01;
6'b100101: fullAdd_0_lut = 2'b10;
6'b111001: fullAdd_0_lut = 2'b01;
6'b011001: fullAdd_0_lut = 2'b10;
6'b101001: fullAdd_0_lut = 2'b11;
6'b111110: fullAdd_0_lut = 2'b11;
6'b011110: fullAdd_0_lut = 2'b01;
6'b101110: fullAdd_0_lut = 2'b10;
6'b110110: fullAdd_0_lut = 2'b01;
6'b010110: fullAdd_0_lut = 2'b10;
6'b100110: fullAdd_0_lut = 2'b11;
6'b111010: fullAdd_0_lut = 2'b10;
6'b011010: fullAdd_0_lut = 2'b11;
6'b101010: fullAdd_0_lut = 2'b01;
default: fullAdd_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] fullAdd_1_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: fullAdd_1_lut = 2'b11;
6'b011111: fullAdd_1_lut = 2'b11;
6'b101111: fullAdd_1_lut = 2'b01;
6'b110111: fullAdd_1_lut = 2'b11;
6'b010111: fullAdd_1_lut = 2'b01;
6'b100111: fullAdd_1_lut = 2'b01;
6'b111011: fullAdd_1_lut = 2'b01;
6'b011011: fullAdd_1_lut = 2'b01;
6'b101011: fullAdd_1_lut = 2'b01;
6'b111101: fullAdd_1_lut = 2'b11;
6'b011101: fullAdd_1_lut = 2'b01;
6'b101101: fullAdd_1_lut = 2'b01;
6'b110101: fullAdd_1_lut = 2'b01;
6'b010101: fullAdd_1_lut = 2'b01;
6'b100101: fullAdd_1_lut = 2'b01;
6'b111001: fullAdd_1_lut = 2'b01;
6'b011001: fullAdd_1_lut = 2'b01;
6'b101001: fullAdd_1_lut = 2'b10;
6'b111110: fullAdd_1_lut = 2'b01;
6'b011110: fullAdd_1_lut = 2'b01;
6'b101110: fullAdd_1_lut = 2'b01;
6'b110110: fullAdd_1_lut = 2'b01;
6'b010110: fullAdd_1_lut = 2'b01;
6'b100110: fullAdd_1_lut = 2'b10;
6'b111010: fullAdd_1_lut = 2'b01;
6'b011010: fullAdd_1_lut = 2'b10;
6'b101010: fullAdd_1_lut = 2'b10;
default: fullAdd_1_lut = 2'b00;
endcase
end
endfunction

function [1:0] halfAdd_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: halfAdd_0_lut = 2'b10;
6'b011111: halfAdd_0_lut = 2'b11;
6'b101111: halfAdd_0_lut = 2'b01;
6'b110111: halfAdd_0_lut = 2'b11;
6'b010111: halfAdd_0_lut = 2'b01;
6'b100111: halfAdd_0_lut = 2'b10;
6'b111011: halfAdd_0_lut = 2'b01;
6'b011011: halfAdd_0_lut = 2'b10;
6'b101011: halfAdd_0_lut = 2'b11;
6'b111101: halfAdd_0_lut = 2'b10;
6'b011101: halfAdd_0_lut = 2'b11;
6'b101101: halfAdd_0_lut = 2'b01;
6'b110101: halfAdd_0_lut = 2'b11;
6'b010101: halfAdd_0_lut = 2'b01;
6'b100101: halfAdd_0_lut = 2'b10;
6'b111001: halfAdd_0_lut = 2'b01;
6'b011001: halfAdd_0_lut = 2'b10;
6'b101001: halfAdd_0_lut = 2'b11;
6'b111110: halfAdd_0_lut = 2'b10;
6'b011110: halfAdd_0_lut = 2'b11;
6'b101110: halfAdd_0_lut = 2'b01;
6'b110110: halfAdd_0_lut = 2'b11;
6'b010110: halfAdd_0_lut = 2'b01;
6'b100110: halfAdd_0_lut = 2'b10;
6'b111010: halfAdd_0_lut = 2'b01;
6'b011010: halfAdd_0_lut = 2'b10;
6'b101010: halfAdd_0_lut = 2'b11;
default: halfAdd_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] halfAdd_1_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: halfAdd_1_lut = 2'b11;
6'b011111: halfAdd_1_lut = 2'b01;
6'b101111: halfAdd_1_lut = 2'b01;
6'b110111: halfAdd_1_lut = 2'b01;
6'b010111: halfAdd_1_lut = 2'b01;
6'b100111: halfAdd_1_lut = 2'b01;
6'b111011: halfAdd_1_lut = 2'b01;
6'b011011: halfAdd_1_lut = 2'b01;
6'b101011: halfAdd_1_lut = 2'b10;
6'b111101: halfAdd_1_lut = 2'b11;
6'b011101: halfAdd_1_lut = 2'b01;
6'b101101: halfAdd_1_lut = 2'b01;
6'b110101: halfAdd_1_lut = 2'b01;
6'b010101: halfAdd_1_lut = 2'b01;
6'b100101: halfAdd_1_lut = 2'b01;
6'b111001: halfAdd_1_lut = 2'b01;
6'b011001: halfAdd_1_lut = 2'b01;
6'b101001: halfAdd_1_lut = 2'b10;
6'b111110: halfAdd_1_lut = 2'b11;
6'b011110: halfAdd_1_lut = 2'b01;
6'b101110: halfAdd_1_lut = 2'b01;
6'b110110: halfAdd_1_lut = 2'b01;
6'b010110: halfAdd_1_lut = 2'b01;
6'b100110: halfAdd_1_lut = 2'b01;
6'b111010: halfAdd_1_lut = 2'b01;
6'b011010: halfAdd_1_lut = 2'b01;
6'b101010: halfAdd_1_lut = 2'b10;
default: halfAdd_1_lut = 2'b00;
endcase
end
endfunction

function [1:0] neg_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: neg_0_lut = 2'b10;
6'b011111: neg_0_lut = 2'b01;
6'b101111: neg_0_lut = 2'b11;
6'b110111: neg_0_lut = 2'b10;
6'b010111: neg_0_lut = 2'b01;
6'b100111: neg_0_lut = 2'b11;
6'b111011: neg_0_lut = 2'b10;
6'b011011: neg_0_lut = 2'b01;
6'b101011: neg_0_lut = 2'b11;
6'b111101: neg_0_lut = 2'b10;
6'b011101: neg_0_lut = 2'b01;
6'b101101: neg_0_lut = 2'b11;
6'b110101: neg_0_lut = 2'b10;
6'b010101: neg_0_lut = 2'b01;
6'b100101: neg_0_lut = 2'b11;
6'b111001: neg_0_lut = 2'b10;
6'b011001: neg_0_lut = 2'b01;
6'b101001: neg_0_lut = 2'b11;
6'b111110: neg_0_lut = 2'b10;
6'b011110: neg_0_lut = 2'b01;
6'b101110: neg_0_lut = 2'b11;
6'b110110: neg_0_lut = 2'b10;
6'b010110: neg_0_lut = 2'b01;
6'b100110: neg_0_lut = 2'b11;
6'b111010: neg_0_lut = 2'b10;
6'b011010: neg_0_lut = 2'b01;
6'b101010: neg_0_lut = 2'b11;
default: neg_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] sign_0_lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: sign_0_lut = 2'b11;
6'b011111: sign_0_lut = 2'b11;
6'b101111: sign_0_lut = 2'b11;
6'b110111: sign_0_lut = 2'b11;
6'b010111: sign_0_lut = 2'b11;
6'b100111: sign_0_lut = 2'b11;
6'b111011: sign_0_lut = 2'b11;
6'b011011: sign_0_lut = 2'b11;
6'b101011: sign_0_lut = 2'b11;
6'b111101: sign_0_lut = 2'b11;
6'b011101: sign_0_lut = 2'b11;
6'b101101: sign_0_lut = 2'b11;
6'b110101: sign_0_lut = 2'b11;
6'b010101: sign_0_lut = 2'b01;
6'b100101: sign_0_lut = 2'b10;
6'b111001: sign_0_lut = 2'b10;
6'b011001: sign_0_lut = 2'b10;
6'b101001: sign_0_lut = 2'b10;
6'b111110: sign_0_lut = 2'b10;
6'b011110: sign_0_lut = 2'b10;
6'b101110: sign_0_lut = 2'b10;
6'b110110: sign_0_lut = 2'b10;
6'b010110: sign_0_lut = 2'b10;
6'b100110: sign_0_lut = 2'b10;
6'b111010: sign_0_lut = 2'b10;
6'b011010: sign_0_lut = 2'b10;
6'b101010: sign_0_lut = 2'b10;
default: sign_0_lut = 2'b00;
endcase
end
endfunction

function [1:0] constZero__lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: constZero__lut = 2'b01;
6'b011111: constZero__lut = 2'b01;
6'b101111: constZero__lut = 2'b01;
6'b110111: constZero__lut = 2'b01;
6'b010111: constZero__lut = 2'b01;
6'b100111: constZero__lut = 2'b01;
6'b111011: constZero__lut = 2'b01;
6'b011011: constZero__lut = 2'b01;
6'b101011: constZero__lut = 2'b01;
6'b111101: constZero__lut = 2'b01;
6'b011101: constZero__lut = 2'b01;
6'b101101: constZero__lut = 2'b01;
6'b110101: constZero__lut = 2'b01;
6'b010101: constZero__lut = 2'b01;
6'b100101: constZero__lut = 2'b01;
6'b111001: constZero__lut = 2'b01;
6'b011001: constZero__lut = 2'b01;
6'b101001: constZero__lut = 2'b01;
6'b111110: constZero__lut = 2'b01;
6'b011110: constZero__lut = 2'b01;
6'b101110: constZero__lut = 2'b01;
6'b110110: constZero__lut = 2'b01;
6'b010110: constZero__lut = 2'b01;
6'b100110: constZero__lut = 2'b01;
6'b111010: constZero__lut = 2'b01;
6'b011010: constZero__lut = 2'b01;
6'b101010: constZero__lut = 2'b01;
default: constZero__lut = 2'b00;
endcase
end
endfunction

function [1:0] constOne__lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: constOne__lut = 2'b10;
6'b011111: constOne__lut = 2'b10;
6'b101111: constOne__lut = 2'b10;
6'b110111: constOne__lut = 2'b10;
6'b010111: constOne__lut = 2'b10;
6'b100111: constOne__lut = 2'b10;
6'b111011: constOne__lut = 2'b10;
6'b011011: constOne__lut = 2'b10;
6'b101011: constOne__lut = 2'b10;
6'b111101: constOne__lut = 2'b10;
6'b011101: constOne__lut = 2'b10;
6'b101101: constOne__lut = 2'b10;
6'b110101: constOne__lut = 2'b10;
6'b010101: constOne__lut = 2'b10;
6'b100101: constOne__lut = 2'b10;
6'b111001: constOne__lut = 2'b10;
6'b011001: constOne__lut = 2'b10;
6'b101001: constOne__lut = 2'b10;
6'b111110: constOne__lut = 2'b10;
6'b011110: constOne__lut = 2'b10;
6'b101110: constOne__lut = 2'b10;
6'b110110: constOne__lut = 2'b10;
6'b010110: constOne__lut = 2'b10;
6'b100110: constOne__lut = 2'b10;
6'b111010: constOne__lut = 2'b10;
6'b011010: constOne__lut = 2'b10;
6'b101010: constOne__lut = 2'b10;
default: constOne__lut = 2'b00;
endcase
end
endfunction

function [1:0] constMin__lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: constMin__lut = 2'b11;
6'b011111: constMin__lut = 2'b11;
6'b101111: constMin__lut = 2'b11;
6'b110111: constMin__lut = 2'b11;
6'b010111: constMin__lut = 2'b11;
6'b100111: constMin__lut = 2'b11;
6'b111011: constMin__lut = 2'b11;
6'b011011: constMin__lut = 2'b11;
6'b101011: constMin__lut = 2'b11;
6'b111101: constMin__lut = 2'b11;
6'b011101: constMin__lut = 2'b11;
6'b101101: constMin__lut = 2'b11;
6'b110101: constMin__lut = 2'b11;
6'b010101: constMin__lut = 2'b11;
6'b100101: constMin__lut = 2'b11;
6'b111001: constMin__lut = 2'b11;
6'b011001: constMin__lut = 2'b11;
6'b101001: constMin__lut = 2'b11;
6'b111110: constMin__lut = 2'b11;
6'b011110: constMin__lut = 2'b11;
6'b101110: constMin__lut = 2'b11;
6'b110110: constMin__lut = 2'b11;
6'b010110: constMin__lut = 2'b11;
6'b100110: constMin__lut = 2'b11;
6'b111010: constMin__lut = 2'b11;
6'b011010: constMin__lut = 2'b11;
6'b101010: constMin__lut = 2'b11;
default: constMin__lut = 2'b00;
endcase
end
endfunction

function [1:0] nullifyTrue__lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b101111: nullifyTrue__lut = 2'b11;
6'b100111: nullifyTrue__lut = 2'b01;
6'b101011: nullifyTrue__lut = 2'b10;
6'b101101: nullifyTrue__lut = 2'b11;
6'b100101: nullifyTrue__lut = 2'b01;
6'b101001: nullifyTrue__lut = 2'b10;
6'b101110: nullifyTrue__lut = 2'b11;
6'b100110: nullifyTrue__lut = 2'b01;
6'b101010: nullifyTrue__lut = 2'b10;
default: nullifyTrue__lut = 2'b00;
endcase
end
endfunction

function [1:0] nullifyFalse__lut(
input [1:0] p0
, input [1:0] p1
, input [1:0] p2
);
begin
case ({p0, p1, p2})
6'b111111: nullifyFalse__lut = 2'b11;
6'b110111: nullifyFalse__lut = 2'b01;
6'b111011: nullifyFalse__lut = 2'b10;
6'b111101: nullifyFalse__lut = 2'b11;
6'b110101: nullifyFalse__lut = 2'b01;
6'b111001: nullifyFalse__lut = 2'b10;
6'b111110: nullifyFalse__lut = 2'b11;
6'b110110: nullifyFalse__lut = 2'b01;
6'b111010: nullifyFalse__lut = 2'b10;
default: nullifyFalse__lut = 2'b00;
endcase
end
endfunction


function [1:0] cmp_1(
input [1:0] lhs
, input [1:0] rhs
);
begin
cmp_1 = cmp_0_lut(lhs, rhs, lhs);
end
endfunction

function [1:0] equal_1(
input [1:0] lhs
, input [1:0] rhs
);
begin
equal_1 = equal_0_lut(lhs, rhs, lhs);
end
endfunction

function [3:0] fullAdd_1(
input [1:0] lhs
, input [1:0] rhs
, input [1:0] carry
);
reg [1:0] v_3;
reg [1:0] v_4;

begin
v_3 = fullAdd_0_lut(lhs, rhs, carry);
v_4 = fullAdd_1_lut(lhs, rhs, carry);
fullAdd_1 = { v_3, v_4 };
end
endfunction

function [3:0] halfAdd_1(
input [1:0] val
, input [1:0] carry
);
reg [1:0] v_2;
reg [1:0] v_3;

begin
v_2 = halfAdd_0_lut(val, carry, val);
v_3 = halfAdd_1_lut(val, carry, val);
halfAdd_1 = { v_2, v_3 };
end
endfunction

function [1:0] neg_1(
input [1:0] val
);
begin
neg_1 = neg_0_lut(val, val, val);
end
endfunction

function [1:0] sign_1(
input [1:0] val
);
begin
sign_1 = val;
end
endfunction

function [5:0] constZero_3(
input [1:0] v_0
);
begin
constZero_3 = { constZero__lut(v_0, v_0, v_0), constZero__lut(v_0, v_0, v_0), constZero__lut(v_0, v_0, v_0) };
end
endfunction

function [17:0] constZero_9(
input [1:0] v_0
);
begin
constZero_9 = { constZero_3(v_0), constZero_3(v_0), constZero_3(v_0) };
end
endfunction

function [35:0] constZero_18(
input [1:0] v_0
);
begin
constZero_18 = { constZero_9(v_0), constZero_9(v_0) };
end
endfunction

function [11:0] constZero_6(
input [1:0] v_0
);
begin
constZero_6 = { constZero_3(v_0), constZero_3(v_0) };
end
endfunction

function [1:0] constZero_1(
input [1:0] v_0
);
begin
constZero_1 = constZero__lut(v_0, v_0, v_0);
end
endfunction

function [49:0] constZero_25(
input [1:0] v_0
);
begin
constZero_25 = { constZero_18(v_0), constZero_6(v_0), constZero_1(v_0) };
end
endfunction

function [53:0] const_27_T1(
input [1:0] v_0
);
reg [1:0] v_1;
reg [1:0] v_2;
reg [49:0] v_3;

begin
v_1 = constMin__lut(v_0, v_0, v_0);
v_2 = constOne__lut(v_0, v_0, v_0);
v_3 = constZero_25(v_0);
const_27_T1 = { v_1, v_2, v_3 };
end
endfunction

function [1:0] cmp_3(
input [5:0] lhs
, input [5:0] rhs
);
reg [1:0] v_2;
reg [1:0] v_3;
reg [1:0] val0;
reg [1:0] v_5;
reg [1:0] v_6;
reg [1:0] val1;
reg [1:0] v_8;
reg [1:0] v_9;
reg [1:0] val2;

begin
v_2 = lhs[5:4];
v_3 = rhs[5:4];
val0 = cmp_0_lut(v_2, v_3, v_2);
v_5 = lhs[3:2];
v_6 = rhs[3:2];
val1 = cmp_0_lut(v_5, v_6, v_5);
v_8 = lhs[1:0];
v_9 = rhs[1:0];
val2 = cmp_0_lut(v_8, v_9, v_8);
cmp_3 = sign_0_lut(val0, val1, val2);
end
endfunction

0 Kudos
Observer dck140130
Observer
628 Views
Registered: ‎02-06-2018

Re: Failed Synthesis, and Elaboration for recursive function call in Vivado 2017.4

Jump to solution

function [1:0] cmp_9(
input [17:0] lhs
, input [17:0] rhs
);
reg [5:0] v_2;
reg [5:0] v_3;
reg [1:0] val0;
reg [5:0] v_5;
reg [5:0] v_6;
reg [1:0] val1;
reg [5:0] v_8;
reg [5:0] v_9;
reg [1:0] val2;

begin
v_2 = lhs[17:12];
v_3 = rhs[17:12];
val0 = cmp_3(v_2, v_3);
v_5 = lhs[11:6];
v_6 = rhs[11:6];
val1 = cmp_3(v_5, v_6);
v_8 = lhs[5:0];
v_9 = rhs[5:0];
val2 = cmp_3(v_8, v_9);
cmp_9 = sign_0_lut(val0, val1, val2);
end
endfunction

function [1:0] cmp_27(
input [53:0] lhs
, input [53:0] rhs
);
reg [17:0] v_2;
reg [17:0] v_3;
reg [1:0] val0;
reg [17:0] v_5;
reg [17:0] v_6;
reg [1:0] val1;
reg [17:0] v_8;
reg [17:0] v_9;
reg [1:0] val2;

begin
v_2 = lhs[53:36];
v_3 = rhs[53:36];
val0 = cmp_9(v_2, v_3);
v_5 = lhs[35:18];
v_6 = rhs[35:18];
val1 = cmp_9(v_5, v_6);
v_8 = lhs[17:0];
v_9 = rhs[17:0];
val2 = cmp_9(v_8, v_9);
cmp_27 = sign_0_lut(val0, val1, val2);
end
endfunction

function [5:0] nullifyTrue_3(
input [1:0] v_0
, input [5:0] v_1
);
reg [1:0] v_2;
reg [1:0] v_3;
reg [1:0] v_4;

begin
v_2 = v_1[5:4];
v_3 = v_1[3:2];
v_4 = v_1[1:0];
nullifyTrue_3 = { nullifyTrue__lut(v_0, v_2, v_2), nullifyTrue__lut(v_0, v_3, v_3), nullifyTrue__lut(v_0, v_4, v_4) };
end
endfunction

function [17:0] nullifyTrue_9(
input [1:0] v_0
, input [17:0] v_1
);
reg [5:0] v_2;
reg [5:0] v_3;
reg [5:0] v_4;

begin
v_2 = v_1[17:12];
v_3 = v_1[11:6];
v_4 = v_1[5:0];
nullifyTrue_9 = { nullifyTrue_3(v_0, v_2), nullifyTrue_3(v_0, v_3), nullifyTrue_3(v_0, v_4) };
end
endfunction

function [53:0] nullifyTrue_27(
input [1:0] v_0
, input [53:0] v_1
);
reg [17:0] v_2;
reg [17:0] v_3;
reg [17:0] v_4;

begin
v_2 = v_1[53:36];
v_3 = v_1[35:18];
v_4 = v_1[17:0];
nullifyTrue_27 = { nullifyTrue_9(v_0, v_2), nullifyTrue_9(v_0, v_3), nullifyTrue_9(v_0, v_4) };
end
endfunction

function [5:0] nullifyFalse_3(
input [1:0] v_0
, input [5:0] v_1
);
reg [1:0] v_2;
reg [1:0] v_3;
reg [1:0] v_4;

begin
v_2 = v_1[5:4];
v_3 = v_1[3:2];
v_4 = v_1[1:0];
nullifyFalse_3 = { nullifyFalse__lut(v_0, v_2, v_2), nullifyFalse__lut(v_0, v_3, v_3), nullifyFalse__lut(v_0, v_4, v_4) };
end
endfunction

function [17:0] nullifyFalse_9(
input [1:0] v_0
, input [17:0] v_1
);
reg [5:0] v_2;
reg [5:0] v_3;
reg [5:0] v_4;

begin
v_2 = v_1[17:12];
v_3 = v_1[11:6];
v_4 = v_1[5:0];
nullifyFalse_9 = { nullifyFalse_3(v_0, v_2), nullifyFalse_3(v_0, v_3), nullifyFalse_3(v_0, v_4) };
end
endfunction

function [53:0] nullifyFalse_27(
input [1:0] v_0
, input [53:0] v_1
);
reg [17:0] v_2;
reg [17:0] v_3;
reg [17:0] v_4;

begin
v_2 = v_1[53:36];
v_3 = v_1[35:18];
v_4 = v_1[17:0];
nullifyFalse_27 = { nullifyFalse_9(v_0, v_2), nullifyFalse_9(v_0, v_3), nullifyFalse_9(v_0, v_4) };
end
endfunction

function [1:0] const_1_T(
input [1:0] v_0
);
reg [1:0] v_1;

begin
v_1 = constMin__lut(v_0, v_0, v_0);
const_1_T = v_1;
end
endfunction

function [7:0] halfAdd_3(
input [5:0] val
, input [1:0] carry
);
reg [1:0] v_2;
reg [3:0] add0;
reg [1:0] v_4;
reg [1:0] v_5;
reg [3:0] add1;
reg [1:0] v_7;
reg [1:0] v_8;
reg [3:0] add2;
reg [1:0] v_10;
reg [1:0] v_11;

begin
v_2 = val[5:4];
add0 = halfAdd_1(v_2, carry);
v_4 = val[3:2];
v_5 = add0[1:0];
add1 = halfAdd_1(v_4, v_5);
v_7 = val[1:0];
v_8 = add1[1:0];
add2 = halfAdd_1(v_7, v_8);
v_10 = add0[3:2];
v_11 = add1[3:2];
halfAdd_3 = { v_10, v_11, add2 };
end
endfunction

function [19:0] halfAdd_9(
input [17:0] val
, input [1:0] carry
);
reg [5:0] v_2;
reg [7:0] add0;
reg [5:0] v_4;
reg [1:0] v_5;
reg [7:0] add1;
reg [5:0] v_7;
reg [1:0] v_8;
reg [7:0] add2;
reg [5:0] v_10;
reg [5:0] v_11;

begin
v_2 = val[17:12];
add0 = halfAdd_3(v_2, carry);
v_4 = val[11:6];
v_5 = add0[1:0];
add1 = halfAdd_3(v_4, v_5);
v_7 = val[5:0];
v_8 = add1[1:0];
add2 = halfAdd_3(v_7, v_8);
v_10 = add0[7:2];
v_11 = add1[7:2];
halfAdd_9 = { v_10, v_11, add2 };
end
endfunction

function [55:0] halfAdd_27(
input [53:0] val
, input [1:0] carry
);
reg [17:0] v_2;
reg [19:0] add0;
reg [17:0] v_4;
reg [1:0] v_5;
reg [19:0] add1;
reg [17:0] v_7;
reg [1:0] v_8;
reg [19:0] add2;
reg [17:0] v_10;
reg [17:0] v_11;

begin
v_2 = val[53:36];
add0 = halfAdd_9(v_2, carry);
v_4 = val[35:18];
v_5 = add0[1:0];
add1 = halfAdd_9(v_4, v_5);
v_7 = val[17:0];
v_8 = add1[1:0];
add2 = halfAdd_9(v_7, v_8);
v_10 = add0[19:2];
v_11 = add1[19:2];
halfAdd_27 = { v_10, v_11, add2 };
end
endfunction

function [53:0] decr_27(
input [53:0] val
);
reg [1:0] v_1;
reg [55:0] halfSum;

begin
v_1 = const_1_T(val[1:0]);
halfSum = halfAdd_27(val, v_1);
decr_27 = halfSum[55:2];
end
endfunction

function [5:0] neg_3(
input [5:0] val
);
reg [1:0] v_1;
reg [1:0] val0;
reg [1:0] v_3;
reg [1:0] val1;
reg [1:0] v_5;
reg [1:0] val2;

begin
v_1 = val[5:4];
val0 = neg_0_lut(v_1, v_1, v_1);
v_3 = val[3:2];
val1 = neg_0_lut(v_3, v_3, v_3);
v_5 = val[1:0];
val2 = neg_0_lut(v_5, v_5, v_5);
neg_3 = { val0, val1, val2 };
end
endfunction

function [17:0] neg_9(
input [17:0] val
);
reg [5:0] v_1;
reg [5:0] val0;
reg [5:0] v_3;
reg [5:0] val1;
reg [5:0] v_5;
reg [5:0] val2;

begin
v_1 = val[17:12];
val0 = neg_3(v_1);
v_3 = val[11:6];
val1 = neg_3(v_3);
v_5 = val[5:0];
val2 = neg_3(v_5);
neg_9 = { val0, val1, val2 };
end
endfunction

function [53:0] neg_27(
input [53:0] val
);
reg [17:0] v_1;
reg [17:0] val0;
reg [17:0] v_3;
reg [17:0] val1;
reg [17:0] v_5;
reg [17:0] val2;

begin
v_1 = val[53:36];
val0 = neg_9(v_1);
v_3 = val[35:18];
val1 = neg_9(v_3);
v_5 = val[17:0];
val2 = neg_9(v_5);
neg_27 = { val0, val1, val2 };
end
endfunction

function [7:0] fullAdd_3(
input [5:0] lhs
, input [5:0] rhs
, input [1:0] carry
);
reg [1:0] v_3;
reg [1:0] v_4;
reg [3:0] add0;
reg [1:0] v_6;
reg [1:0] v_7;
reg [1:0] v_8;
reg [3:0] add1;
reg [1:0] v_10;
reg [1:0] v_11;
reg [1:0] v_12;
reg [3:0] add2;
reg [1:0] v_14;
reg [1:0] v_15;

begin
v_3 = lhs[5:4];
v_4 = rhs[5:4];
add0 = fullAdd_1(v_3, v_4, carry);
v_6 = lhs[3:2];
v_7 = rhs[3:2];
v_8 = add0[1:0];
add1 = fullAdd_1(v_6, v_7, v_8);
v_10 = lhs[1:0];
v_11 = rhs[1:0];
v_12 = add1[1:0];
add2 = fullAdd_1(v_10, v_11, v_12);
v_14 = add0[3:2];
v_15 = add1[3:2];
fullAdd_3 = { v_14, v_15, add2 };
end
endfunction

function [19:0] fullAdd_9(
input [17:0] lhs
, input [17:0] rhs
, input [1:0] carry
);
reg [5:0] v_3;
reg [5:0] v_4;
reg [7:0] add0;
reg [5:0] v_6;
reg [5:0] v_7;
reg [1:0] v_8;
reg [7:0] add1;
reg [5:0] v_10;
reg [5:0] v_11;
reg [1:0] v_12;
reg [7:0] add2;
reg [5:0] v_14;
reg [5:0] v_15;

begin
v_3 = lhs[17:12];
v_4 = rhs[17:12];
add0 = fullAdd_3(v_3, v_4, carry);
v_6 = lhs[11:6];
v_7 = rhs[11:6];
v_8 = add0[1:0];
add1 = fullAdd_3(v_6, v_7, v_8);
v_10 = lhs[5:0];
v_11 = rhs[5:0];
v_12 = add1[1:0];
add2 = fullAdd_3(v_10, v_11, v_12);
v_14 = add0[7:2];
v_15 = add1[7:2];
fullAdd_9 = { v_14, v_15, add2 };
end
endfunction

function [55:0] fullAdd_27(
input [53:0] lhs
, input [53:0] rhs
, input [1:0] carry
);
reg [17:0] v_3;
reg [17:0] v_4;
reg [19:0] add0;
reg [17:0] v_6;
reg [17:0] v_7;
reg [1:0] v_8;
reg [19:0] add1;
reg [17:0] v_10;
reg [17:0] v_11;
reg [1:0] v_12;
reg [19:0] add2;
reg [17:0] v_14;
reg [17:0] v_15;

begin
v_3 = lhs[53:36];
v_4 = rhs[53:36];
add0 = fullAdd_9(v_3, v_4, carry);
v_6 = lhs[35:18];
v_7 = rhs[35:18];
v_8 = add0[1:0];
add1 = fullAdd_9(v_6, v_7, v_8);
v_10 = lhs[17:0];
v_11 = rhs[17:0];
v_12 = add1[1:0];
add2 = fullAdd_9(v_10, v_11, v_12);
v_14 = add0[19:2];
v_15 = add1[19:2];
fullAdd_27 = { v_14, v_15, add2 };
end
endfunction

function [53:0] sub_27(
input [53:0] lhs
, input [53:0] rhs
);
reg [53:0] v_2;
reg [1:0] v_3;
reg [55:0] sum;

begin
v_2 = neg_27(rhs);
v_3 = constZero_1(lhs[1:0]);
sum = fullAdd_27(lhs, v_2, v_3);
sub_27 = sum[55:2];
end
endfunction

function [53:0] add_27(
input [53:0] lhs
, input [53:0] rhs
);
reg [1:0] v_2;
reg [55:0] sum;

begin
v_2 = constZero_1(lhs[1:0]);
sum = fullAdd_27(lhs, rhs, v_2);
add_27 = sum[55:2];
end
endfunction

function automatic [53:0] fibonacci1_27(
input [53:0] n
);
reg [53:0] v_1;
reg [1:0] v_2;
reg [1:0] retN;
reg [53:0] v_4;
reg [53:0] v_5;
reg [53:0] nMin1;
reg [53:0] v_7;
reg [53:0] v_8;
reg [53:0] v_9;
reg [53:0] v_10;
reg [53:0] nMin2;
reg [53:0] v_12;
reg [53:0] v_13;

begin
v_1 = const_27_T1(n[1:0]);
v_2 = cmp_27(n, v_1);
retN = isLess_0_lut(v_2, v_2, v_2);
v_4 = nullifyTrue_27(retN, n);
v_5 = nullifyFalse_27(retN, n);
nMin1 = decr_27(v_5);
v_7 = fibonacci1_27(nMin1);
v_8 = nullifyFalse_27(retN, n);
v_9 = const_27_T1(n[1:0]);
v_10 = nullifyFalse_27(retN, v_9);
nMin2 = sub_27(v_8, v_10);
v_12 = fibonacci1_27(nMin2);
v_13 = add_27(v_7, v_12);
fibonacci1_27 = merge__27(v_4, v_13);
end
endfunction

function [53:0] constZero_27(
input [1:0] v_0
);
begin
constZero_27 = { constZero_9(v_0), constZero_9(v_0), constZero_9(v_0) };
end
endfunction

function [51:0] constZero_26(
input [1:0] v_0
);
begin
constZero_26 = { constZero_25(v_0), constZero_1(v_0) };
end
endfunction

function [53:0] const_27_1(
input [1:0] v_0
);
reg [1:0] v_1;
reg [51:0] v_2;

begin
v_1 = constOne__lut(v_0, v_0, v_0);
v_2 = constZero_26(v_0);
const_27_1 = { v_1, v_2 };
end
endfunction

function [1:0] sign_3(
input [5:0] val
);
reg [1:0] v_1;
reg [1:0] v_2;
reg [1:0] v_3;

begin
v_1 = val[5:4];
v_2 = val[3:2];
v_3 = val[1:0];
sign_3 = sign_0_lut(v_1, v_2, v_3);
end
endfunction

function [1:0] sign_9(
input [17:0] val
);
reg [5:0] v_1;
reg [1:0] val0;
reg [5:0] v_3;
reg [1:0] val1;
reg [5:0] v_5;
reg [1:0] val2;

begin
v_1 = val[17:12];
val0 = sign_3(v_1);
v_3 = val[11:6];
val1 = sign_3(v_3);
v_5 = val[5:0];
val2 = sign_3(v_5);
sign_9 = sign_0_lut(val0, val1, val2);
end
endfunction

function [1:0] sign_27(
input [53:0] val
);
reg [17:0] v_1;
reg [1:0] val0;
reg [17:0] v_3;
reg [1:0] val1;
reg [17:0] v_5;
reg [1:0] val2;

begin
v_1 = val[53:36];
val0 = sign_9(v_1);
v_3 = val[35:18];
val1 = sign_9(v_3);
v_5 = val[17:0];
val2 = sign_9(v_5);
sign_27 = sign_0_lut(val0, val1, val2);
end
endfunction

function automatic [53:0] fibPart2_27(
input [53:0] n
, input [53:0] fib0
, input [53:0] fib1
);
reg [1:0] v_3;
reg [1:0] retFib2;
reg [53:0] fib2;
reg [53:0] v_6;
reg [53:0] v_7;
reg [53:0] v_8;
reg [53:0] v_9;
reg [53:0] v_10;
reg [53:0] v_11;

begin
v_3 = sign_27(n);
retFib2 = isZero_0_lut(v_3, v_3, v_3);
fib2 = add_27(fib0, fib1);
v_6 = nullifyTrue_27(retFib2, fib2);
v_7 = nullifyFalse_27(retFib2, n);
v_8 = decr_27(v_7);
v_9 = nullifyFalse_27(retFib2, fib1);
v_10 = nullifyFalse_27(retFib2, fib2);
v_11 = fibPart2_27(v_8, v_9, v_10);
fibPart2_27 = merge__27(v_6, v_11);
end
endfunction

function [53:0] fibonacci2_27(
input [53:0] n
);
reg [53:0] v_1;
reg [1:0] v_2;
reg [1:0] retN;
reg [53:0] v_4;
reg [53:0] v_5;
reg [53:0] v_6;
reg [53:0] v_7;
reg [53:0] v_8;
reg [53:0] v_9;
reg [53:0] v_10;
reg [53:0] v_11;
reg [53:0] v_12;
reg [53:0] v_13;

begin
v_1 = const_27_T1(n[1:0]);
v_2 = cmp_27(n, v_1);
retN = isLess_0_lut(v_2, v_2, v_2);
v_4 = nullifyTrue_27(retN, n);
v_5 = nullifyFalse_27(retN, n);
v_6 = const_27_T1(n[1:0]);
v_7 = nullifyFalse_27(retN, v_6);
v_8 = sub_27(v_5, v_7);
v_9 = constZero_27(n[1:0]);
v_10 = nullifyFalse_27(retN, v_9);
v_11 = const_27_1(n[1:0]);
v_12 = nullifyFalse_27(retN, v_11);
v_13 = fibPart2_27(v_8, v_10, v_12);
fibonacci2_27 = merge__27(v_4, v_13);
end
endfunction

function [107:0] constZero_54(
input [1:0] v_0
);
begin
constZero_54 = { constZero_27(v_0), constZero_27(v_0) };
end
endfunction

function [157:0] constZero_79(
input [1:0] v_0
);
begin
constZero_79 = { constZero_54(v_0), constZero_25(v_0) };
end
endfunction

function [161:0] const_81_T1(
input [1:0] v_0
);
reg [1:0] v_1;
reg [1:0] v_2;
reg [157:0] v_3;

begin
v_1 = constMin__lut(v_0, v_0, v_0);
v_2 = constOne__lut(v_0, v_0, v_0);
v_3 = constZero_79(v_0);
const_81_T1 = { v_1, v_2, v_3 };
end
endfunction

function [1:0] cmp_81(
input [161:0] lhs
, input [161:0] rhs
);
reg [53:0] v_2;
reg [53:0] v_3;
reg [1:0] val0;
reg [53:0] v_5;
reg [53:0] v_6;
reg [1:0] val1;
reg [53:0] v_8;
reg [53:0] v_9;
reg [1:0] val2;

begin
v_2 = lhs[161:108];
v_3 = rhs[161:108];
val0 = cmp_27(v_2, v_3);
v_5 = lhs[107:54];
v_6 = rhs[107:54];
val1 = cmp_27(v_5, v_6);
v_8 = lhs[53:0];
v_9 = rhs[53:0];
val2 = cmp_27(v_8, v_9);
cmp_81 = sign_0_lut(val0, val1, val2);
end
endfunction

function [161:0] nullifyTrue_81(
input [1:0] v_0
, input [161:0] v_1
);
reg [53:0] v_2;
reg [53:0] v_3;
reg [53:0] v_4;

begin
v_2 = v_1[161:108];
v_3 = v_1[107:54];
v_4 = v_1[53:0];
nullifyTrue_81 = { nullifyTrue_27(v_0, v_2), nullifyTrue_27(v_0, v_3), nullifyTrue_27(v_0, v_4) };
end
endfunction

function [161:0] nullifyFalse_81(
input [1:0] v_0
, input [161:0] v_1
);
reg [53:0] v_2;
reg [53:0] v_3;
reg [53:0] v_4;

begin
v_2 = v_1[161:108];
v_3 = v_1[107:54];
v_4 = v_1[53:0];
nullifyFalse_81 = { nullifyFalse_27(v_0, v_2), nullifyFalse_27(v_0, v_3), nullifyFalse_27(v_0, v_4) };
end
endfunction

function [161:0] neg_81(
input [161:0] val
);
reg [53:0] v_1;
reg [53:0] val0;
reg [53:0] v_3;
reg [53:0] val1;
reg [53:0] v_5;
reg [53:0] val2;

begin
v_1 = val[161:108];
val0 = neg_27(v_1);
v_3 = val[107:54];
val1 = neg_27(v_3);
v_5 = val[53:0];
val2 = neg_27(v_5);
neg_81 = { val0, val1, val2 };
end
endfunction

function [163:0] fullAdd_81(
input [161:0] lhs
, input [161:0] rhs
, input [1:0] carry
);
reg [53:0] v_3;
reg [53:0] v_4;
reg [55:0] add0;
reg [53:0] v_6;
reg [53:0] v_7;
reg [1:0] v_8;
reg [55:0] add1;
reg [53:0] v_10;
reg [53:0] v_11;
reg [1:0] v_12;
reg [55:0] add2;
reg [53:0] v_14;
reg [53:0] v_15;

begin
v_3 = lhs[161:108];
v_4 = rhs[161:108];
add0 = fullAdd_27(v_3, v_4, carry);
v_6 = lhs[107:54];
v_7 = rhs[107:54];
v_8 = add0[1:0];
add1 = fullAdd_27(v_6, v_7, v_8);
v_10 = lhs[53:0];
v_11 = rhs[53:0];
v_12 = add1[1:0];
add2 = fullAdd_27(v_10, v_11, v_12);
v_14 = add0[55:2];
v_15 = add1[55:2];
fullAdd_81 = { v_14, v_15, add2 };
end
endfunction

function [161:0] sub_81(
input [161:0] lhs
, input [161:0] rhs
);
reg [161:0] v_2;
reg [1:0] v_3;
reg [163:0] sum;

begin
v_2 = neg_81(rhs);
v_3 = constZero_1(lhs[1:0]);
sum = fullAdd_81(lhs, v_2, v_3);
sub_81 = sum[163:2];
end
endfunction

function [161:0] constZero_81(
input [1:0] v_0
);
begin
constZero_81 = { constZero_27(v_0), constZero_27(v_0), constZero_27(v_0) };
end
endfunction

function [159:0] constZero_80(
input [1:0] v_0
);
begin
constZero_80 = { constZero_79(v_0), constZero_1(v_0) };
end
endfunction

function [161:0] const_81_1(
input [1:0] v_0
);
reg [1:0] v_1;
reg [159:0] v_2;

begin
v_1 = constOne__lut(v_0, v_0, v_0);
v_2 = constZero_80(v_0);
const_81_1 = { v_1, v_2 };
end
endfunction

function [1:0] sign_81(
input [161:0] val
);
reg [53:0] v_1;
reg [1:0] val0;
reg [53:0] v_3;
reg [1:0] val1;
reg [53:0] v_5;
reg [1:0] val2;

begin
v_1 = val[161:108];
val0 = sign_27(v_1);
v_3 = val[107:54];
val1 = sign_27(v_3);
v_5 = val[53:0];
val2 = sign_27(v_5);
sign_81 = sign_0_lut(val0, val1, val2);
end
endfunction

function [161:0] add_81(
input [161:0] lhs
, input [161:0] rhs
);
reg [1:0] v_2;
reg [163:0] sum;

begin
v_2 = constZero_1(lhs[1:0]);
sum = fullAdd_81(lhs, rhs, v_2);
add_81 = sum[163:2];
end
endfunction

function [163:0] halfAdd_81(
input [161:0] val
, input [1:0] carry
);
reg [53:0] v_2;
reg [55:0] add0;
reg [53:0] v_4;
reg [1:0] v_5;
reg [55:0] add1;
reg [53:0] v_7;
reg [1:0] v_8;
reg [55:0] add2;
reg [53:0] v_10;
reg [53:0] v_11;

begin
v_2 = val[161:108];
add0 = halfAdd_27(v_2, carry);
v_4 = val[107:54];
v_5 = add0[1:0];
add1 = halfAdd_27(v_4, v_5);
v_7 = val[53:0];
v_8 = add1[1:0];
add2 = halfAdd_27(v_7, v_8);
v_10 = add0[55:2];
v_11 = add1[55:2];
halfAdd_81 = { v_10, v_11, add2 };
end
endfunction

function [161:0] decr_81(
input [161:0] val
);
reg [1:0] v_1;
reg [163:0] halfSum;

begin
v_1 = const_1_T(val[1:0]);
halfSum = halfAdd_81(val, v_1);
decr_81 = halfSum[163:2];
end
endfunction

function automatic [161:0] fibPart2_81(
input [161:0] n
, input [161:0] fib0
, input [161:0] fib1
);
reg [1:0] v_3;
reg [1:0] retFib2;
reg [161:0] fib2;
reg [161:0] v_6;
reg [161:0] v_7;
reg [161:0] v_8;
reg [161:0] v_9;
reg [161:0] v_10;
reg [161:0] v_11;

begin
v_3 = sign_81(n);
retFib2 = isZero_0_lut(v_3, v_3, v_3);
fib2 = add_81(fib0, fib1);
v_6 = nullifyTrue_81(retFib2, fib2);
v_7 = nullifyFalse_81(retFib2, n);
v_8 = decr_81(v_7);
v_9 = nullifyFalse_81(retFib2, fib1);
v_10 = nullifyFalse_81(retFib2, fib2);
v_11 = fibPart2_81(v_8, v_9, v_10);
fibPart2_81 = merge__81(v_6, v_11);
end
endfunction

function automatic [161:0] fibonacci2_81(
input [161:0] n
);
reg [161:0] v_1;
reg [1:0] v_2;
reg [1:0] retN;
reg [161:0] v_4;
reg [161:0] v_5;
reg [161:0] v_6;
reg [161:0] v_7;
reg [161:0] v_8;
reg [161:0] v_9;
reg [161:0] v_10;
reg [161:0] v_11;
reg [161:0] v_12;
reg [161:0] v_13;

begin
v_1 = const_81_T1(n[1:0]);
v_2 = cmp_81(n, v_1);
retN = isLess_0_lut(v_2, v_2, v_2);
v_4 = nullifyTrue_81(retN, n);
v_5 = nullifyFalse_81(retN, n);
v_6 = const_81_T1(n[1:0]);
v_7 = nullifyFalse_81(retN, v_6);
v_8 = sub_81(v_5, v_7);
v_9 = constZero_81(n[1:0]);
v_10 = nullifyFalse_81(retN, v_9);
v_11 = const_81_1(n[1:0]);
v_12 = nullifyFalse_81(retN, v_11);
v_13 = fibPart2_81(v_8, v_10, v_12);
fibonacci2_81 = merge__81(v_4, v_13);
end
endfunction

function [3:0] constZero_2(
input [1:0] v_0
);
begin
constZero_2 = { constZero__lut(v_0, v_0, v_0), constZero__lut(v_0, v_0, v_0) };
end
endfunction

function [1:0] nullifyTrue_1(
input [1:0] v_0
, input [1:0] v_1
);
begin
nullifyTrue_1 = nullifyTrue__lut(v_0, v_1, v_1);
end
endfunction

function [3:0] nullifyTrue_2(
input [1:0] v_0
, input [3:0] v_1
);
reg [1:0] v_2;
reg [1:0] v_3;

begin
v_2 = v_1[3:2];
v_3 = v_1[1:0];
nullifyTrue_2 = { nullifyTrue__lut(v_0, v_2, v_2), nullifyTrue__lut(v_0, v_3, v_3) };
end
endfunction

function [11:0] nullifyTrue_6(
input [1:0] v_0
, input [11:0] v_1
);
reg [5:0] v_2;
reg [5:0] v_3;

begin
v_2 = v_1[11:6];
v_3 = v_1[5:0];
nullifyTrue_6 = { nullifyTrue_3(v_0, v_2), nullifyTrue_3(v_0, v_3) };
end
endfunction

function [35:0] nullifyTrue_18(
input [1:0] v_0
, input [35:0] v_1
);
reg [17:0] v_2;
reg [17:0] v_3;

begin
v_2 = v_1[35:18];
v_3 = v_1[17:0];
nullifyTrue_18 = { nullifyTrue_9(v_0, v_2), nullifyTrue_9(v_0, v_3) };
end
endfunction

function [107:0] nullifyTrue_54(
input [1:0] v_0
, input [107:0] v_1
);
reg [53:0] v_2;
reg [53:0] v_3;

begin
v_2 = v_1[107:54];
v_3 = v_1[53:0];
nullifyTrue_54 = { nullifyTrue_27(v_0, v_2), nullifyTrue_27(v_0, v_3) };
end
endfunction

function [1:0] nullifyFalse_1(
input [1:0] v_0
, input [1:0] v_1
);
begin
nullifyFalse_1 = nullifyFalse__lut(v_0, v_1, v_1);
end
endfunction

function [3:0] nullifyFalse_2(
input [1:0] v_0
, input [3:0] v_1
);
reg [1:0] v_2;
reg [1:0] v_3;

begin
v_2 = v_1[3:2];
v_3 = v_1[1:0];
nullifyFalse_2 = { nullifyFalse__lut(v_0, v_2, v_2), nullifyFalse__lut(v_0, v_3, v_3) };
end
endfunction

function [11:0] nullifyFalse_6(
input [1:0] v_0
, input [11:0] v_1
);
reg [5:0] v_2;
reg [5:0] v_3;

begin
v_2 = v_1[11:6];
v_3 = v_1[5:0];
nullifyFalse_6 = { nullifyFalse_3(v_0, v_2), nullifyFalse_3(v_0, v_3) };
end
endfunction

function [35:0] nullifyFalse_18(
input [1:0] v_0
, input [35:0] v_1
);
reg [17:0] v_2;
reg [17:0] v_3;

begin
v_2 = v_1[35:18];
v_3 = v_1[17:0];
nullifyFalse_18 = { nullifyFalse_9(v_0, v_2), nullifyFalse_9(v_0, v_3) };
end
endfunction

function [107:0] nullifyFalse_54(
input [1:0] v_0
, input [107:0] v_1
);
reg [53:0] v_2;
reg [53:0] v_3;

begin
v_2 = v_1[107:54];
v_3 = v_1[53:0];
nullifyFalse_54 = { nullifyFalse_27(v_0, v_2), nullifyFalse_27(v_0, v_3) };
end
endfunction

function [1:0] merge__1(
input [1:0] input1
, input [1:0] input2
);
begin
case ({input1, input2})
4'b0000: merge__1 = 2'b00;
4'b0001: merge__1 = 2'b01;
4'b0010: merge__1 = 2'b10;
4'b0011: merge__1 = 2'b11;
4'b0100: merge__1 = 2'b01;
4'b1000: merge__1 = 2'b10;
4'b1100: merge__1 = 2'b11;
4'b0101: merge__1 = 2'b01;
4'b1010: merge__1 = 2'b10;
4'b1111: merge__1 = 2'b11;
default: begin
merge__1 = 2'b00;
x = 1;
end
endcase
end
endfunction

function [5:0] merge__3(
input [5:0] input1
, input [5:0] input2
);
reg [1:0] p0;
reg [1:0] p1;
reg [1:0] p2;
begin
p0 = merge__1(input1[5:4], input2[5:4]);
p1 = merge__1(input1[3:2], input2[3:2]);
p2 = merge__1(input1[1:0], input2[1:0]);
merge__3 = { p0, p1, p2 };
end
endfunction

function [17:0] merge__9(
input [17:0] input1
, input [17:0] input2
);
reg [5:0] p0;
reg [5:0] p1;
reg [5:0] p2;
begin
p0 = merge__3(input1[17:12], input2[17:12]);
p1 = merge__3(input1[11:6], input2[11:6]);
p2 = merge__3(input1[5:0], input2[5:0]);
merge__9 = { p0, p1, p2 };
end
endfunction

function [53:0] merge__27(
input [53:0] input1
, input [53:0] input2
);
reg [17:0] p0;
reg [17:0] p1;
reg [17:0] p2;
begin
p0 = merge__9(input1[53:36], input2[53:36]);
p1 = merge__9(input1[35:18], input2[35:18]);
p2 = merge__9(input1[17:0], input2[17:0]);
merge__27 = { p0, p1, p2 };
end
endfunction

function [161:0] merge__81(
input [161:0] input1
, input [161:0] input2
);
reg [53:0] p0;
reg [53:0] p1;
reg [53:0] p2;
begin
p0 = merge__27(input1[161:108], input2[161:108]);
p1 = merge__27(input1[107:54], input2[107:54]);
p2 = merge__27(input1[53:0], input2[53:0]);
merge__81 = { p0, p1, p2 };
end
endfunction

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Scholar markcurry
Scholar
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Registered: ‎09-16-2009

Re: Failed Synthesis, and Elaboration for recursive function call in Vivado 2017.4

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@dck140130

Can you simplify your example? - it's really much too large to diagnose in such a forum.  I can't even quickly pick our where the recursion is. 

Regards,

Mark

Observer dck140130
Observer
453 Views
Registered: ‎02-06-2018

Re: Failed Synthesis, and Elaboration for recursive function call in Vivado 2017.4

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Thank you for taking a look Mark, I will work something simplified up after Thursday :-)
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Moderator
Moderator
415 Views
Registered: ‎03-16-2017

Re: Failed Synthesis, and Elaboration for recursive function call in Vivado 2017.4

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Hi @dck140130,

I have sent you ezmove ftp testpackage. Through which you can provide your archived project. So we can investigate it further.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
Observer dck140130
Observer
381 Views
Registered: ‎02-06-2018

Re: Failed Synthesis, and Elaboration for recursive function call in Vivado 2017.4

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Thank you,

 

Working on this now.

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Observer dck140130
Observer
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Registered: ‎02-06-2018

Re: Failed Synthesis, and Elaboration for recursive function call in Vivado 2017.4/2018.3

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Hi Mark,

My apologies for the delay!

I am attaching a drastically simplified example. Please also see pg 253 of vivado synthesis guide 2018.3 for Vivado provided specs.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis.pdf

Please let me know if you have any luck or advice :)

Cheers,

Don

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Scholar markcurry
Scholar
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Registered: ‎09-16-2009

Re: Failed Synthesis, and Elaboration for recursive function call in Vivado 2017.4/2018.3

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Don,

Your problem here is in the fact that Vivado must know the loop depth (or iteration depth, or recursion depth) as a constant at elaboration time.

What this means (in iteration case) is the loop must be able to be unrolled.

In the recursion case, it means that the arguments to the recursive function must be CONSTANTS at elaboration time.

This has nothing to do with labeling the function as automatic - your results will be the same either way - you don't need an automatic for this function

This example will work in Vivado:

module fact1
(
  input  wire clk_i,
  input  wire reset_i,
  output wire [ 7 : 0 ] fact0_o,
  output wire [ 7 : 0 ] fact1_o
);
  function [ 7 : 0 ] factorial( input [ 7 : 0 ] i_Num );
    if( i_Num == 1 )
      factorial = 1; 
    else
      factorial = i_Num * factorial( i_Num-1 );
  endfunction
  assign fact0_o = factorial( 8'd4 );  // 0x18
  assign fact1_o = factorial( 8'd5 );  // 0x78
endmodule

This will not:

module fact2
(
  input  wire clk_i,
  input  wire reset_i,
  input  wire [ 7 : 0 ] fact_i,
  output wire [ 7 : 0 ] fact_o
);
  function [ 7 : 0 ] factorial( input [ 7 : 0 ] i_Num );
    if( i_Num == 1 )
      factorial = 1; 
    else
      factorial = i_Num * factorial( i_Num-1 );
  endfunction
  assign fact0_o = factorial( fact_i );  
endmodule

Vivado is building hardware - it must build enough hardware as the worse case input requires.  So, it must be able to easily calculate the worse case recursion depth.  Xilinx engineers actually do a good job here of enabling all this to work with constants.  There could be a possible way perhaps of them calculating the maximum recursion depth in the general case - perhaps based on the bit lengths of the recursive function arguments - but that sounds fraught with peril to me.  I think it's wise that the tool is operating as it is.

If you want a generic factorial function, you'll need to write it differently with these limitations in mind.

Regards,

Mark

 

Observer dck140130
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Registered: ‎02-06-2018

Re: Failed Synthesis, and Elaboration for recursive function call in Vivado 2017.4/2018.3

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Mark,

I can not thank you enough for the time you have taken.

I thought I already understood what you are explaining about the instantiation for each round of the function, and that the default recursion depth described in the vivado 2018.3 synthesis guide of 64 rounds would have the same effect that providing input values does in the synthesizable module you provided. I also thought that since our programs will have a global parameter limiting number of computations in a given time period, that I could manually set the recursion limit using the command "-recursion_iteration_limit" that vivado does not seem to recognize. Am I exhibiting a lack of understanding in any obvious way with this line of reasoning, or is it possible that this feature in Vivado (the webpack version) is not operating properly? If it was operating properly, I would expect for only the number of instantiations that the recursion iteration limit is set to.

As an aside, have you looked at the synthesis design? I am not versed on how to read the floorplan, but I am not seeing multiple instantiations. Does it offer you any insights that may be inconspicous to me?

 

With great appreciation to you and Xilinx engineers,

Don

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Scholar markcurry
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Registered: ‎09-16-2009

Re: Failed Synthesis, and Elaboration for recursive function call in Vivado 2017.4/2018.3

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To be fair, I wasn't aware of the "recursion_iteration_limit" argument, nor do I really understand what the switch would do.

I tried my example "fact1" above, with something that required more than 64 depth recursion.  It's still worked fine.  Although I didn't check if the result of 66! was accurate - that's a big number - would require 309 bits  - although the function as written only keeps the lower 8.

So I'm not sure wat that switch is doing. Perhaps in other recursive cases  - factorial is a bad example - where there's variable, and constant arguments.  The constant arguments could be used by the tool to determine recursion depth, but the variable arguments would affect the function? (total guess on my part).  Maybe in those instances, the tool's limited to "recursion_iteration_limit" depths?  I dunno.  I'd play around with other recursive functions perhaps to shed some light here, if you're curious and have need.

In any event, for the examples I provided - the only one that works "fact1.v" produces no logic at all.  The result is a constant - all the output ports will just be tied off 1 or 0.

Regards,

Mark