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1,612 Views
Registered: ‎03-12-2018

Falling edge Clocked code produces LUT on clock line

We are having timing problems caused by a LUT being put on a Clock line to invert it rather than using an inverted clock Flip-Flop.

 

Why are the tools doing this?  Are we out of Flip-Flops that support an inverted clock? Is our code somehow responsible (reset inside of Clock block?

 

Our code is similar to the following:

 

 

 process(i_SysClk)
    begin
        if falling_edge(i_SysClk) then
            if i_InternalReset = '0' then
                r_ADCWordCount <= 0;
                ...

            else
                if (i_ADCWritePtr /= r_PrevADCWritePtr) and (i_ADCReadPtr = r_PrevADCReadPtr) then 
                        r_ADCWordCount <= r_ADCWordCount + 1;
                elsif (i_ADCReadPtr /= r_PrevADCReadPtr) and (i_ADCWritePtr = r_PrevADCWritePtr) then 
                   if r_ADCWordCount > i_ADCWordsPerBuffer then
                        r_ADCWordCount <= i_ADCWordsPerBuffer - 1;
                    elsif r_ADCWordCount - 1 >= 0 then
                        r_ADCWordCount <= r_ADCWordCount - 1;
                    else
                        r_ADCWordCount <= 0;
                    end if; end if;
...
end if;

We have seen this several times now and would like to know what we are doing so we can avoid this.

 

Please let me know if there is more detail or information I can provide.

 

Thank you.

 

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7 Replies
Scholar jmcclusk
Scholar
1,607 Views
Registered: ‎02-24-2014

Re: Falling edge Clocked code produces LUT on clock line

Falling edge to rising edge timing essentially cuts your timing margin in half.   Or equivalently, it's like doubling your clock speed, so it's not surprising that you are having timing problems.     But just flipping the polarity of this process from falling edge to rising edge is likely to have consequences elsewhere, especially if this code is involved in a specific data capture circuit to external devices.    If this is entirely internal, then why does this code use the falling edge at all?   There must be some design reason to use this.

Don't forget to close a thread when possible by accepting a post as a solution.
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1,602 Views
Registered: ‎03-12-2018

Re: Falling edge Clocked code produces LUT on clock line

Yes, there are design reasons to have this on the falling edge.  This is probably not directly our issue. Our system clock is running at 128MHz or about 7.8ns period. 

 

The issue we have is that the tool is putting the Clock through a lut to invert it and this causes significant enough delays that timing is not met when the output of this flip-flop goes to another one that has the non-inverted clock.

 

In other locations of the design the falling edge detection is synthesized by the tools directly on a flip-flop with an inverted clock pin and so the delay is less than running it through a LUT.

 

What I would like to know is why it uses a LUT for inversion in some areas and in other areas it uses an inverted clock pin on the flip-flop.

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Explorer
Explorer
1,584 Views
Registered: ‎09-07-2011

Re: Falling edge Clocked code produces LUT on clock line

What device?

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Xilinx Employee
Xilinx Employee
1,545 Views
Registered: ‎07-21-2014

Re: Falling edge Clocked code produces LUT on clock line

Hi,

In synthesis there looks to be some issue with detecting falling edge flipflops particularly with the 'if elsif else' ladder and so it is inferring LUT in the clock path. However if you run opt_design on your synthesized design, it should be able to pull the LUT and infer -ve edge flipflop.
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Highlighted
Explorer
Explorer
1,532 Views
Registered: ‎09-07-2011

Re: Falling edge Clocked code produces LUT on clock line

Vivado synthesizer?

 

Shot in the dark, wonder if this style avoids it, since the clock edge is not snarled up in the if-elsif-etc.

 

process --(i_SysClk)
    begin
        wait until falling_edge (i_SysClk);

            if i_InternalReset = '0' then
                r_ADCWordCount <= 0;
                ...

            else
                if (i_ADCWritePtr /= r_PrevADCWritePtr) and (i_ADCReadPtr = r_PrevADCReadPtr) then 
                        r_ADCWordCount <= r_ADCWordCount + 1;
                elsif (i_ADCReadPtr /= r_PrevADCReadPtr) and (i_ADCWritePtr = .....
                ...
end process;
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1,514 Views
Registered: ‎03-12-2018

Re: Falling edge Clocked code produces LUT on clock line

to aher: So are you saying that you think if we run an optimization on the synthesized design it would change how it is inferring the LUT?  We have tried various combinations of strategies for both Synthesis and Implementation but we don't have a good grasp on what Strategy we should be using, it is more of a trial and error process right now so any guidance in that area might be useful as well.

 

We are building for an Artix 7 part using Vivado 2017.4.

 

We can try using a different construct rather than If else type ones so see what happens but I guess we are still left to see if there are timing errors somewhere to see if this issue exists in other areas of the design as well.  How could I find out if a LUT was being put on a clock line if it didn't fail timing, or should we care?

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Xilinx Employee
Xilinx Employee
1,282 Views
Registered: ‎07-21-2014

Re: Falling edge Clocked code produces LUT on clock line

Hi,

Sorry for the late reply.
Yes, all LUTs (used for inversion of clock) should be optimized and negative edge flop should be inferred after running optimization. Do you still see LUT for clock inversion after running implementation?

Coming to the strategy- Description of synthesis strategies is tabulated in UG901 under section "Vivado Preconfigured Strategies". This essentially changes values of switches and directives used for synthesis. You can at first keep it default. Change the value as per your design requirement as per the description
In case of implementation, first you should try to meet all timing goals using vivado default strategy. But if you are unable to, You can primarily try performance explore at the cost of run time increase. Other strategies description you can find in UG904 implementation User Guide -Appendix C

For the third part, if needed, we can find out if there are still any LUTs left on clock path using tcl script. Do you see/suspect timing failures because of this?

-Shreyas
----------------------------------------------------------------------------------------------
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Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
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