UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor cv330
Visitor
1,894 Views
Registered: ‎02-24-2018

Finite State Machine Strange Syntesis

Jump to solution

Hi everybody,

 

I'm having some troubles in my project, in particular I'm not meeting timing and I get the following "no clock" message in the report:

 (Photo 1)

 

Initially I didn't understood why there was this report because I didn't used those signals nor components, so I opened the schematic of the finite state machine I've created in my project and this weird design came out: 

(Photos 2 to 6)

 

This schematic seem to me very strange, there are latches, falling-edge-triggered FF, adders, mults and many components that I can't explain to myself why exist in the circuit, and in addiction they cause problems in timing. The code of the FSM is the following, please let me understand what's happening because I really can't and excuse me for the long post and the many photos. 

Thank you in advance for the collaboration.

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity statemachine is
  Port (start,thre,clk : in std_logic;
        ce: out std_logic;
        sel : out std_logic_vector(1 downto 0));
end statemachine;

architecture Behavioral of statemachine is


    type state_type is (s0,s1,s2,setup,stop);
    signal next_state : state_type;
    signal current_state : state_type:= setup;
    
begin
    state_decode_proc : process (current_state,start,thre)
    begin
        case current_state is
            when setup =>
                if (start = '1') then
                    next_state <= s0;
                else
                    next_state <= setup;
                end if;
            when s0 =>
             next_state <= s1;
            when s1 =>
             next_state <= s2;
                
            when s2 =>
                if (thre = '1') then
                    next_state <= stop;
                else
                    next_state <= s0;
                end if;
            when stop =>
                  assert FALSE report "end simulation" severity failure;
        end case;
    end process;
    
    state_proc : process(clk)
    begin
    if rising_edge(clk) then
            current_state <= next_state;
            end if;
    end process;
    
    output_proc : process (current_state)
    begin
        case current_state is
            when s0 => 
                ce <= '1';
                sel <= "01";
            when s1 =>
                ce <= '1';
                sel <= "10";
            when s2 =>
                ce <= '1';
                sel <= "00";               
            when setup =>
                ce <= '0';
            when stop =>
                   assert FALSE report "end simulation" severity failure;
        end case;
    end process;




end Behavioral;

 

Tags (1)
Schermata del 2018-02-24 16-50-04.png
fsm1.png
Schermata del 2018-02-24 17-00-45.png
Schermata del 2018-02-24 17-02-36.png
Schermata del 2018-02-24 17-02-54.png
Schermata del 2018-02-24 17-03-04.png
0 Kudos
1 Solution

Accepted Solutions
Visitor cv330
Visitor
2,541 Views
Registered: ‎02-24-2018

Re: Finite State Machine Strange Syntesis

Jump to solution

I've solved the problem myself. I've used the normal single clock process for the state machine. Then with some multipexers I've obtained the result I wanted in the circuit.

 

Thanks for the answers to all, they were very helpful. We can now close this thread.

8 Replies
Explorer
Explorer
1,863 Views
Registered: ‎09-07-2011

Re: Finite State Machine Strange Syntesis

Jump to solution

The state_decode and output_proc processes probably infer latches.  In the 'stop' state for example, no values are given for the signals they drive, plus ce and sel are not fully described.

 

Probably easiest just to do one process:

 

state_proc : process (clk)
    begin
        if rising_edge(clk) then

        case state is
            when setup =>
ce <= '0';
sel <= "00";
if (start = '1') then state <= s0; end if; when s0 =>
ce <= '1';
sel <= "01"; state <= s1;
when s1 => ..... end case;

end if;--clock end process;
0 Kudos
Voyager
Voyager
1,854 Views
Registered: ‎06-20-2017

Re: Finite State Machine Strange Syntesis

Jump to solution

I assume this is for school.  I wish professors would stop teaching 2 and 3 process state machines, which are so 1996.

 

Here is some code, but I didn't test it.   Modify it until it does what you want.  Keep your monitoring in your testbench.  E.g., using the assert severity failure to end the simulation.

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity statemachine is
  port (
    iStart : IN  std_logic;
    iThre  : IN  std_logic;
    iCLK   : IN  std_logic;
    oCE    : OUT std_logic;
    oSel   : OUT std_logic_vector(1 downto 0)
   );
end entity statemachine;

architecture rtl of statemachine is

    type state_type is (
      FSM_S0,     -- renameme
      FSM_S1,     -- renameme
      FSM_S2,     -- renameme
      FSM_SETUP,
      FSM_STOP
    );
    signal FSM_STATE : state_type:= FSM_SETUP;
    
begin
    
  -- Note:  You will have to recode this, this is
  --        just an example
  FSM_PROC : process(iCLK)
  begin
    if rising_edge(iCLK) then
      case FSM_STATE is
        when FSM_SETUP =>
          oCE  <= '0';
          oSel <= "--"; --fixme
          if (iStart = '1') then
            FSM_STATE <= FSM_S0;
          else
            FSM_STATE <= FSM_SETUP;
          end if;
  
        when FSM_S0 =>
          oCE  <= '1';
          oSel <= "01";
          FSM_STATE <= FSM_S1;
  
        when FSM_S1 =>
          FSM_STATE <= FSM_S2;
          oCE <= '1';
          oSel <= "10";
          
        when FSM_S2 =>
          oCE <= '1';
          oSel <= "00";   
          if (iThre = '1') then
            FSM_STATE <= FSM_STOP;
          else
            FSM_STATE <= FSM_S0;
          end if;
  
        when FSM_STOP =>
          oCE  <= '-'; --fixme 
          oSel <= "--"; --fixme        
          -- put this in your testbench: assert FALSE report "end simulation" severity failure;
      end case;
    end if;
  end process FSM_PROC;
    
end architecture rtl;
Mike
Visitor cv330
Visitor
1,808 Views
Registered: ‎02-24-2018

Re: Finite State Machine Strange Syntesis

Jump to solution

YESSS!!

It worked, all "no clock" messages are gone. And yes this is for school and the 3 process state machine was teached me by my professor... Thank you very much for bringing me back to 2018!

 

Now I want to ask another question. If I would make a state machine that changes state at every edge of the clock, would be enough to write if (clk'event and clock='0' and clock ='1' ) instead of rising_edge(clk) or I have to make another specular process triggered on falling_edge(clk) or whatever?

0 Kudos
Mentor hgleamon1
Mentor
1,778 Views
Registered: ‎11-14-2011

Re: Finite State Machine Strange Syntesis

Jump to solution

Why would you want to change state at every clock state change?

 

if (clk'event and clock='0' and clock ='1' )

 

Just think for a short a while about why this statement literally makes no sense.

 

Also, think about your design as HARDWARE. What special type of flipflop do you have availabe that can operate on both clock edges?

----------
"That which we must learn to do, we learn by doing." - Aristotle
0 Kudos
Visitor cv330
Visitor
1,766 Views
Registered: ‎02-24-2018

Re: Finite State Machine Strange Syntesis

Jump to solution

I've figured out that the if(clk'event ...etc..) statement make no sense and i've changed approach.

I want to change state at every clock state change because this fsm is driving a circuit that works on both edges using dual-edge-triggered registers made out of 2 flip-flops which output is multiplexed in base of the clock. For this and others purposes I'm using 2 clocks out of phase of 180° and i've written this new statement , which anyway is giving me some problems:

 

process(CLKUP,CLKDOWN)

begin

 if (rising_edge(CLKUP) or rising_edge(CLKDOWN) ) then

...

...etc..

 

Should I use two different processes for each clock o should I have to modify this?

Can you suggest me some solutions or some tips, please? 

0 Kudos
Mentor hgleamon1
Mentor
1,758 Views
Registered: ‎11-14-2011

Re: Finite State Machine Strange Syntesis

Jump to solution

The issue is you are still gating the clock input to a flipflop and this is not good.

 

If you really must use both edges of the clock (and, apart from DDR applications where there are defined methods of approach) you'd have to have two separate process for each edge of the clock

 

I can see no value in doing this - you understand that you will be making it harder for yourself to meet timing by effectively halving the clock period?

 

What is the application/circuit that requires both edges of the clock?

----------
"That which we must learn to do, we learn by doing." - Aristotle
0 Kudos
Visitor cv330
Visitor
2,542 Views
Registered: ‎02-24-2018

Re: Finite State Machine Strange Syntesis

Jump to solution

I've solved the problem myself. I've used the normal single clock process for the state machine. Then with some multipexers I've obtained the result I wanted in the circuit.

 

Thanks for the answers to all, they were very helpful. We can now close this thread.

Mentor hgleamon1
Mentor
1,711 Views
Registered: ‎11-14-2011

Re: Finite State Machine Strange Syntesis

Jump to solution

Good that you solved your issue. You need to accept some answer as the solution to formally close the thread. I suggest accepting your own final post for this.

----------
"That which we must learn to do, we learn by doing." - Aristotle
0 Kudos