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9,410 Views
Registered: ‎02-08-2012

For generate statement with a calculated index

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Hi,

 

Please can you help me in corecting this program ?

i want to genetate a set of components using a parameterized index

 

Thanks in advance

 

-- switch 4 ports
switch4x4 : if number_of_ports = 4 generate
switch_4x4:for i in 1 to number_of_ports generate
shared variable j:natural;
begin
--j=number_of_ports*(i-1);
PORTx4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
GENERIC MAP(number_of_ports =>4)
PORT MAP(
data_in => Port_in(i),
data_in_en => data_in_en(i),
reset => reset,
clk =>clk,
grant(number_of_ports*(i-1)+1) => grant_signal(number_of_ports*(i-1)+1),
grant(number_of_ports*(i-1)+2) => grant_signal(number_of_ports*(i-1)+2),
grant(number_of_ports*(i-1)+3) => grant_signal(number_of_ports*(i-1)+3),
grant(number_of_ports*(i-1)+4) => grant_signal(number_of_ports*(i-1)+4),
fifo_full =>fifo_in_full(i),
priority_rotation => priority_rotation_signal(i),
fifo_empty => fifo_in_empty(i),
data_out =>crossbar_in_port(i),
data_out_pulse =>crossbar_in_pulse(i),
request(number_of_ports*(i-1)+1) =>request_signal(number_of_ports*(i-1)+1),
request(number_of_ports*(i-1)+2) =>request_signal(number_of_ports*(i-1)+2),
request(number_of_ports*(i-1)+3) =>request_signal(number_of_ports*(i-1)+3),
request(number_of_ports*(i-1)+4) =>request_signal(number_of_ports*(i-1)+4)
);
end generate switch_4x4;
end generate switch4x4;

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1 Solution

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Historian
Historian
11,932 Views
Registered: ‎02-25-2008

Re: For generate statement with a calculated index

Jump to solution

@herver wrote:
didn't jump to me earlier but "Bad association for formal port request" points to the lines ...
request(16) =>request_signal(j+16)

I don't know the VHDL rules by heart but I don't think you can write that, in fact it doesn't look right...
I think you need to assign the whole bus at once rather than individual bits/slice of bus.
Do you also get the error about grant to?

For the bus: can't you try the full bus: request =>request_signal(j+16 downto j+1)?

You can assign individual members of a vector in a port map.

I think I see his problem.

 

His component declaration shows the vector declared as:

 

    grant : in std_logic_vector(NUMBER_OF_PORTS downto 1);

 

where NUMBER_OF_PORTS is set with the generic to 4.

 

But the instantiation shows eight individual maps to the port vector grant:

 

      grant(1) => grant_signal(j+1);

    grant(2) => grant_signal(j+2);

    grant(3) => grant_signal(j+3);

    grant(4) => grant_signal(j+4);

    grant(5) => grant_signal(j+5);

    grant(6) => grant_signal(j+6);

    grant(7) => grant_signal(j+7);

    grant(8) => grant_signal(j+8);

 

I suspect that XST throws the error at analysis (compilation) time. At that point, it only knows the component interface, and it uses the default for the generic NUMBER_OF_PORTS. That default, of course, is 4, and he's trying to map an 8-bit vector, and the analyzer barfs on that.

 

Using the expression

 

    grant =>grant(j+16 downto j+1);

 

won't help, either, because there's an assumption that the vector is always 16 bits wide.

 

Something like:

 

    grant => grant(j+NUMBER_OF_PORTS downto j + 1);

 

might be better.

 

Having said all of that: the VHDL guru might leave the grant and request vectors unconstrained, in the INPUT_PORT_MODULE component's port list. The instantiating entity needs to declare a signal of the desired width, and when that signal is used as the actual in the port map, the size of the vector is automatically known to the instantiated entity. Then the engineer can use attributes ('LEFT, 'LENGTH, whatever) to handle the variable size of the vectors in the INPUT_PORT_MODULE entity.

 

So there it is.

----------------------------Yes, I do this for a living.
11 Replies
Teacher rcingham
Teacher
9,399 Views
Registered: ‎09-09-2010

Re: For generate statement with a calculated index

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"Please can you help me in correcting this program?"

It isn't a "program", it's a "hardware description"!

Does it apparently not work in simulation, or in synthesis?
If in simulation, post compiler error messages, or waveforms with description about what is wrong with the behaviour.
If in synthesis, state FPGA type and ISE version, and post the error messages.


------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Xilinx Employee
Xilinx Employee
9,398 Views
Registered: ‎08-17-2011

Re: For generate statement with a calculated index

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Hello Gamomchristian,

What's the issue ?
Do you have any error and what needs correcting?

Did you ask somebody in your team/school?
It would help if you post the full entity and inner modules. So that it's easy to put through XST;
What happens if number_of_ports is NOT 4 ?
What gets generated in that case?

(sorry crossed with R's post above)

- Hervé

SIGNATURE:
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* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.
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9,388 Views
Registered: ‎02-08-2012

Re: For generate statement with a calculated index

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Thanks for your intererest on my post,

 

Here below is the next part of the code

i've changed the way j is declared.  j is now a constant and i notice that the previous error ( has disappear

The whole code may be too long for a post.

i'm trying to generate a parameterized Noc

the number of ports is a generic parameter of the entity

i just posted part of the architecture.

the purpose of my achitecture is to generate an interconnect the components i wish to use.

 

the new error is :

ERROR:Xst:751 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 1026: Bad association for formal port 'request' of component 'INPUT_PORT_MODULE'.
-----------

--declaration sections

COMPONENT INPUT_PORT_MODULE
generic(number_of_ports : positive := 4);
Port ( data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_in_en : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
request : out STD_LOGIC_VECTOR (number_of_ports downto 1);
grant : in STD_LOGIC_VECTOR (number_of_ports downto 1);
fifo_full : out STD_LOGIC;
fifo_empty : out STD_LOGIC;
priority_rotation : out std_logic;
data_out : out STD_LOGIC_VECTOR (7 downto 0);
data_out_pulse : out std_logic);
END COMPONENT;

Signal Request_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);

....

----------

--- architecture section causing problem
switch8x8 : if number_of_ports = 8 generate
switch_8x8:for i in 1 to number_of_ports generate
constant j: natural:=number_of_ports*(i-1);
begin
--j<=number_of_ports*(i-1);
PORTx8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
GENERIC MAP(number_of_ports =>4)
PORT MAP(
data_in => Port_in(i),
data_in_en => data_in_en(i),
reset => reset,
clk =>clk,
grant(1) => grant_signal(j+1),
grant(2) => grant_signal(j+2),
grant(3) => grant_signal(j+3),
grant(4) => grant_signal(j+4),
grant(5) => grant_signal(j+5),
grant(6) => grant_signal(j+6),
grant(7) => grant_signal(j+7),
grant(8) => grant_signal(j+8),
fifo_full =>fifo_in_full(i),
priority_rotation => priority_rotation_signal(i),
fifo_empty => fifo_in_empty(i),
data_out =>crossbar_in_port(i),
data_out_pulse =>crossbar_in_pulse(i),
request(1) =>request_signal(j+1),
request(2) =>request_signal(j+2),
request(3) =>request_signal(j+3),
request(4) =>request_signal(j+4),
request(5) =>request_signal(j+5),
request(6) =>request_signal(j+6),
request(7) =>request_signal(j+7),
request(8) =>request_signal(j+8)
);
end generate switch_8x8;
end generate switch8x8;

-- switch 16 ports
switch16x16 : if number_of_ports = 16 generate
switch_16x16 :for i in 1 to number_of_ports generate
Constant j : natural:=number_of_ports*(i-1);
begin
--j<=number_of_ports*(i-1);
PORTx16_INPUT_PORT_MODULE: INPUT_PORT_MODULE
GENERIC MAP(number_of_ports =>16)
PORT MAP(
data_in => Port_in(i),
data_in_en => data_in_en(i),
reset => reset,
clk =>clk,
grant(1) => grant_signal(j+1),
grant(2) => grant_signal(j+2),
grant(3) => grant_signal(j+3),
grant(4) => grant_signal(j+4),
grant(5) => grant_signal(j+5),
grant(6) => grant_signal(j+6),
grant(7) => grant_signal(j+7),
grant(8) => grant_signal(j+8),
grant(9) => grant_signal(j+9),
grant(10) => grant_signal(j+10),
grant(11) => grant_signal(j+11),
grant(12) => grant_signal(j+12),
grant(13) => grant_signal(j+13),
grant(14) => grant_signal(j+14),
grant(15) => grant_signal(j+15),
grant(16) => grant_signal(j+16),
fifo_full =>fifo_in_full(i),
priority_rotation => priority_rotation_signal(i),
fifo_empty => fifo_in_empty(i),
data_out =>crossbar_in_port(i),
data_out_pulse =>crossbar_in_pulse(i),
request(1) =>request_signal(j+1),
request(2) =>request_signal(j+2),
request(3) =>request_signal(j+3),
request(4) =>request_signal(j+4),
request(5) =>request_signal(j+5),
request(6) =>request_signal(j+6),
request(7) =>request_signal(j+7),
request(8) =>request_signal(j+8),
request(9) =>request_signal(j+9),
request(10) =>request_signal(j+10),
request(11) =>request_signal(j+11),
request(12) =>request_signal(j+12),
request(13) =>request_signal(j+13),
request(14) =>request_signal(j+14),
request(15) =>request_signal(j+15),
request(16) =>request_signal(j+16)
);
end generate switch_16x16;
end generate switch16x16;

 

 

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Xilinx Employee
Xilinx Employee
9,379 Views
Registered: ‎08-17-2011

Re: For generate statement with a calculated index

Jump to solution
didn't jump to me earlier but "Bad association for formal port request" points to the lines ...
request(16) =>request_signal(j+16)

I don't know the VHDL rules by heart but I don't think you can write that, in fact it doesn't look right...
I think you need to assign the whole bus at once rather than individual bits/slice of bus.
Do you also get the error about grant to?

For the bus: can't you try the full bus: request =>request_signal(j+16 downto j+1)?
- Hervé

SIGNATURE:
* New Dedicated Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.
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Historian
Historian
11,933 Views
Registered: ‎02-25-2008

Re: For generate statement with a calculated index

Jump to solution

@herver wrote:
didn't jump to me earlier but "Bad association for formal port request" points to the lines ...
request(16) =>request_signal(j+16)

I don't know the VHDL rules by heart but I don't think you can write that, in fact it doesn't look right...
I think you need to assign the whole bus at once rather than individual bits/slice of bus.
Do you also get the error about grant to?

For the bus: can't you try the full bus: request =>request_signal(j+16 downto j+1)?

You can assign individual members of a vector in a port map.

I think I see his problem.

 

His component declaration shows the vector declared as:

 

    grant : in std_logic_vector(NUMBER_OF_PORTS downto 1);

 

where NUMBER_OF_PORTS is set with the generic to 4.

 

But the instantiation shows eight individual maps to the port vector grant:

 

      grant(1) => grant_signal(j+1);

    grant(2) => grant_signal(j+2);

    grant(3) => grant_signal(j+3);

    grant(4) => grant_signal(j+4);

    grant(5) => grant_signal(j+5);

    grant(6) => grant_signal(j+6);

    grant(7) => grant_signal(j+7);

    grant(8) => grant_signal(j+8);

 

I suspect that XST throws the error at analysis (compilation) time. At that point, it only knows the component interface, and it uses the default for the generic NUMBER_OF_PORTS. That default, of course, is 4, and he's trying to map an 8-bit vector, and the analyzer barfs on that.

 

Using the expression

 

    grant =>grant(j+16 downto j+1);

 

won't help, either, because there's an assumption that the vector is always 16 bits wide.

 

Something like:

 

    grant => grant(j+NUMBER_OF_PORTS downto j + 1);

 

might be better.

 

Having said all of that: the VHDL guru might leave the grant and request vectors unconstrained, in the INPUT_PORT_MODULE component's port list. The instantiating entity needs to declare a signal of the desired width, and when that signal is used as the actual in the port map, the size of the vector is automatically known to the instantiated entity. Then the engineer can use attributes ('LEFT, 'LENGTH, whatever) to handle the variable size of the vectors in the INPUT_PORT_MODULE entity.

 

So there it is.

----------------------------Yes, I do this for a living.
Xilinx Employee
Xilinx Employee
9,362 Views
Registered: ‎08-17-2011

Re: For generate statement with a calculated index

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Good observations !- I realized earlier today that effectively you could have individual bits assignments in VHDL.

 

I put my money on you :)

 

note for gamomchristian: it's possible to attach files too since effectively copying 1000 lines is a lot.

- Hervé

SIGNATURE:
* New Dedicated Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.
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9,360 Views
Registered: ‎02-08-2012

Re: For generate statement with a calculated index

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No i didn't get the error with grant signal

 

when i did the change you suggest to me, the error disappear but annother error with the generic parameter number_of_ports was found.

After correcting that error XST compile successfully the design

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9,358 Views
Registered: ‎02-08-2012

Re: For generate statement with a calculated index

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Much tanks
you clearly understood what was my problem
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Xilinx Employee
Xilinx Employee
9,351 Views
Registered: ‎08-17-2011

Re: For generate statement with a calculated index

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Could you give a Kudo to bassman59 - click the rectangle with the star on the right.
- Hervé

SIGNATURE:
* New Dedicated Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.
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Observer moxix2
Observer
1,933 Views
Registered: ‎11-02-2015

Re: For generate statement with a calculated index

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Hi,@bassman59

How to leave std_logic_vector unconstrained in the component port list? Just leave out the range part? I had the same generic problem with a signal, xst prevent me from unconstraining signal with std_logic_vector type.

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Historian
Historian
1,921 Views
Registered: ‎02-25-2008

Re: For generate statement with a calculated index

Jump to solution

@moxix2 wrote:

Hi,@bassman59

How to leave std_logic_vector unconstrained in the component port list? Just leave out the range part? I had the same generic problem with a signal, xst prevent me from unconstraining signal with std_logic_vector type.


Read a VHDL textbook.

 

On the entity's post list, you simple omit the range part:

 

entity foo is

    port (

        ...

        bar : std_logic_vector;

        ...

    );

end entity clif;

 

and in the higher-level entity in which you instantiate foo, you must ensure that the actuals (right-hand-side of the port map) have a size that can be determined at analysis time:

 

    signal higherbar : std_logic_vector(10 downto 0);

 

    u_foo : entity work.foo

        port map (

            ...

            bar => higher_bar,

            ...

    );

 

and it will work.

 

In the entity foo you can use the usual signal attributes ('length, 'left, 'right, etc) if you need to know the actual size of the vector.

 

----------------------------Yes, I do this for a living.
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