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Observer
Observer
4,955 Views
Registered: ‎10-30-2008

For help on the time consumption of ISE

Dear everyone,

 

I am doing an Image Algorithm on V5 SX50t FPGA. As the algorithm requires, I have to use a large number of memory and adders, such as ' reg [7:0] mem[79:0][239:0]; reg [17:0] mem1[79:0] [59:0]'.

 

When I am doing Synthesis and Implement, it takes years. Any advice on improve the XST speed is highly appreciated.

 

BTW: I have noticed that the XST only use 50% of the Core 2 CPU.

 

Many thanks!

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Observer
Observer
4,943 Views
Registered: ‎02-27-2009

You usually run into that kind of thing when the router is trying to route a lot of distributed RAM; it is just a terrifyingly complex problem to route 3495872834579283457982346582734568347 nets all over the chip and still get decent timing out of it (and often impossible!).  Make sure that your design correctly infers a Block RAM primitive as necessary.
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Observer
Observer
4,925 Views
Registered: ‎10-30-2008

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