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Adventurer
Adventurer
409 Views
Registered: ‎01-05-2017

For loop in if clause

Hi,

I'm trying to do "for loop" in an "if elsif" structure and having some issues (some part of the code attached)

I want to keep 24 bit data coming from several other sources in a memory block after cut into 8 bit parts. This is because of the structure of the following sections. 

The synthesis result says:

[Synth 8-3331] design ... has unconnected port Data0[15] and ... Data0[0]. This is same for the other 24 Bit data sources.

I' m trying to simulate the function of the module so need to overcome this issue.

Any idea what is wrong??

 

edit: any advice is also appreciated for (if there is a way ) changing the DataX -> X:0:4 in a for loop maybe?? 

 

Thanks in advance...

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5 Replies
Highlighted
385 Views
Registered: ‎01-22-2015

Re: For loop in if clause

@macellan85 

One problem:  elsif clause shown in red will never get executed because of "if s_index = 2" in first line.

		if s_index = 2 then
			ST_TRANS <= TRANSMISSION_ST ;
			s_we     <='0';
			s_index  <= 0 ;
		else
			if s_index = 0 then
				for i in 0 to 2 loop
					s_addr  <= std_logic_vector(to_unsigned(s_index*3+i, 6));
					s_Data_in <= Data0(8*(i+1)-1 downto 8*i);
				end loop;
			
			elsif s_index = 1 then
				for i in 0 to 2 loop
					s_addr <= std_logic_vector(to_unsigned(s_index*3+i, 6));
					s_Data_in <= Data1(8*(i+1)-1 downto 8*i);
				end loop;
			
			elsif s_index = 2 then
				for i in 0 to 2 loop
					s_addr <= std_logic_vector(to_unsigned(s_index*3+i, 6));
					s_Data_in <= Data2(8*(i+1)-1 downto 8*i);
				end loop;
			
			end if;                        
			s_index  <= s_index + 1;
			
		end if;

Maybe you want:

			if s_index = 0 then
				for i in 0 to 2 loop
					s_addr  <= std_logic_vector(to_unsigned(s_index*3+i, 6));
					s_Data_in <= Data0(8*(i+1)-1 downto 8*i);
				end loop;
			
			elsif s_index = 1 then
				for i in 0 to 2 loop
					s_addr <= std_logic_vector(to_unsigned(s_index*3+i, 6));
					s_Data_in <= Data1(8*(i+1)-1 downto 8*i);
				end loop;
			
			elsif s_index = 2 then
				for i in 0 to 2 loop
					s_addr <= std_logic_vector(to_unsigned(s_index*3+i, 6));
					s_Data_in <= Data2(8*(i+1)-1 downto 8*i);
				end loop;
			
			end if;     
                        
                        if(s_index < 2) then
			       s_index  <= s_index + 1;
                        else
			       ST_TRANS <= TRANSMISSION_ST ;
			       s_we     <='0';
			       s_index  <= 0 ;
                        end if;			

Mark

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Teacher
Teacher
380 Views
Registered: ‎07-09-2009

Re: For loop in if clause

One other point
using if / else is a very bad way of coding this sort of thing
use a case statement
https://www.nandland.com/vhdl/examples/example-case-statement.html
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Adventurer
Adventurer
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Registered: ‎01-05-2017

Re: For loop in if clause

Dear markg@prosensing.com 

Thank you for pointing that. "s_index =2 ". actually it must be 3 at the top. I missed it when trying to shorten the code for uploading here. 

I' ll try to add the second if loop for incrementing the s_index!

 

Dear @drjohnsmith 

Thanks for the suggestion. What do you think about nested case statement? If statements are already inside a case block as in attached file.

 

 

Additionally, I' ll be happy to hear if there is a way to remove all if blocks ( or maybe case blocks ) and use a for loop (or any other kind of loop ) ??  This will make the code more compact.

 

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Teacher
Teacher
335 Views
Registered: ‎07-09-2009

Re: For loop in if clause

My suggestion is to stop thinking about "compact code"

code that is easy to read , and informative is much less error prone and easier to maintain,

Look up one line programming, its compact, but not very useful or easy to maintain

e.g.
main(int c,char**v){return!m(v[1],v[2]);}m(char*s,char*t){return*t-42?*s?63==*t|*s==*t&&m(s+1,t+1):!*t:m(s,t+1)||*s&&m(s+1,t);}

is a real program, !!

https://en.wikipedia.org/wiki/One-liner_program

case within case is quiet valid, and efficient way of programming FPGAs

BUT

it does IMHO often indicate a less than optimised system level design,

At the end of the day, you must remember that you are describing hardware,

VHDL is a Hardware Description Language

think about what hardware you want often helps designing a system,



<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Highlighted
314 Views
Registered: ‎01-22-2015

Re: For loop in if clause

If you are using any of the 2018 releases of Vivado, then beware of the bug described in AR#72586 for case-statements/state-machines.